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EDA tool reduces design time for FinFETs

Posted: 24 Apr 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Mentor Graphics? EDA? FinFET? SoC? Samsung?

Mentor Graphics Corp. has unveiled an EDA tool that is capable of handling parasitic capacitance, resistance and inductance extraction for designers. The Calibre xACT cuts the guesswork and setup by designers, being especially effective for advanced designs using our 14nm FinFET processes, according to Kuang-Kuo Lin, the director of Samsung Semiconductor's foundry marketing ecosystem.

"Calibre xACT speeds up the design flow working with our own Calibre IC verification tools, of course, but will also work with Cadence's and Synopsys' physical design and verification tools," said Carey Robertson, director of product marketing at Mentor Graphics. "It provides better accuracy and faster performance for the newest IC processes, including FinFETs (3D transistors)."

Calibre xACT

Calibre xACT claims to quickly and accurately extract parasitic capacitance, resistance and inductance for IC designs including digital, custom, analogue and RF. (Source: Mentor Graphics)

Calibre xACT will extract capacitive, resistive and inductive values for anything from a single memory or standard cell to a complete SoC. Parasitic extraction is a growing concern for designers especially with complex devices such as FinFETs needing both high accuracy and high-speed on billion transistor SoCs with memory, analogue, standard cell and custom logic all mixed together, according to Mentor.

"Samsung has worked extensively on the Calibre xACT platform with Mentor Graphics," stated Lin. "Because of its high-accuracy it is really helping us on these new processes where FinFET devices require mode complex and accurate modeling, but designers still need fast turnaround time.

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