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TI bares FPGA alternative

Posted: 24 Apr 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Analogue front end? high-speed data? JESD204B?

Texas Instruments announced its 66AK2L06 programmable system-on-chip, a competitive alternative to field-programmable gate arrays (FPGAs) that delivers up to 50 per cent less cost and better power reduction.

The 66AK2L06 SoC integrates the JESD204B interface standard, reducing the overall board footprint by up to 66 per cent. This integration also allows designers in markets such as avionics, defence, medical, and test and measurement to develop products with increased performance and up to 50 per cent lower power. TI cites DSP programmability and pre-validation of multiple high speed ADCs, DACs and AFEs. TI's system level solution is further enabled on the 66AK2L06 SoC by the Multicore Software Development Kit (MCSDK) and RF Software Development Kit (RFSDK).

Extending TI's highly integrated and scalable KeyStone multi-core architecture, the 66AK2L06 SoC integration of a Digital Front End (DFE)/Digital Down Converter-Up Converter (DDUC) and a JESD204B interface delivers a reduction in system cost and power. The integration of TI's DSPs and ARM Cortex processors claims twice the performance of current competing solutions with software programmability. Four TMS320C66x DSP cores, each rated at up to 1.2GHz of signal processing, allow users flexibility in programming via floating point. In order to perform complex control code processing, dual ARM Cortex-A15 MPCore processors deliver up to 1.2GHz of processing power and enable real-time direct access to I/Os with low latency.


A Fast Fourier Transform Coprocessor (FFTC) module is accessible across all the DSP cores to accelerate the FFT and IFFT computations that are required in applications such as radar systems. Additionally, the network coprocessor (NETCP), a hardware accelerator that processes data packets with a main focus on processing Ethernet packets, has four gigabit Ethernet (GbE) modules to send and receive packets from an IEEE 802.3 compliant network, as well as a packet accelerator (PA) to perform packet classification operations such as header matching, and packet modification operations and a security accelerator (SA) to encrypt and decrypt data packets.

The adaptive power technology in 66AK2L06 provides up to 50 per cent lower power than competing devices with cooling requirements. With integrated wideband sample rate conversion and digital filtering up to 48-channels, the 66AK2L06 eliminates the need for an additional device, thus reducing the board area by up to 66 per cent.

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