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Taking advantage of TSMC's 28HPC process

Posted: 30 Apr 2015 ?? ?Print Version ?Bookmark and Share

Keywords:TSMC? system on chips? SoCs? lithography? EDA tools?

Multi-bit flip-flops provide a set of additional flops that have been optimised for power and area with a minor trade-off in performance and placement flexibility. The flops share a common clock pin, which decreases the overall clock loading of the N flops in the multi-bit flop cell, reduces area with a corresponding reduction in leakage, and reduces dynamic power on the clock tree significantly (up to 50% for a dual flop, more for quad or octal) (figure 6).

Multi-bit flip-flops are typically used in blocks that are not in the critical path of the highest chip operating frequency. They range from small, bus-oriented registers of SoC configuration data that are only clocked at power up, to major datapaths that are clocked every cycle and with a number of variants in between. SoC designers use the replacement ratio, measured by how many of the standard flops in the design can be replaced by their multi-bit equivalents and the resulting PPA improvements, to determine their overall chip power and area savings. The single-bit flip-flops to be replaced with multi-bit flip-flops must have the same function (clock edge, set/reset and scan configuration).

As an example, figure 7 shows a 32bit processor being synthesised with a logic library for TSMC 28HPM (blue line) and again with the same library characterized to the TSMC 28HPC process (orange line), where you can see greater performance in less area. Including innovative cells such as those in the Synopsys High Performance Core Design Kit enables SoC designers to achieve smaller area for a given frequency and a higher top end frequency as seen in the dotted orange and blue lines.

Figure 7: Comparison of the 28HPM process with the 28HPC process using Synopsys logic libraries and adding the Synopsys HPC Design Kit libraries to harden a 32bit processor by sweeping timing constraints for a synthesised block until the library can no longer close timing.

Integration with latest digital EDA tool features
Logic libraries for the TSMC 28HPC process must be designed to be synthesised, placed, routed, validated and optimised by digital EDA tools for timing, power and design rule compliance through design flows integrated with synthesis, place and route, design rules constraints and other tools. Digital EDA tools and flows enable designers to take full advantage of the circuit innovations such as multi-bit flops and the compact layouts designed into the most efficient logic libraries.

TSMC's new 28HPC High K Metal Gate process is touted to offer improvements in process rules and variability to enable smaller designs, at higher performances, using less power. Leading synthesis and place and route tools can best take advantage of these process improvements to meet demanding design specifications if they have the right set of logic libraries that take full advantage of these new process capabilities. The Synopsys DesignWare TSMC 28HPC logic libraries and EDA tools are designed to enable SoC designers to push the limits of performance, area and power and fully utilise the capabilities of the TSMC 28HPC process.

About the author
Ken is the Product Marketing Manager for Logic Libraries at Synopsys. He works with advanced node SoC design teams and leading foundries to provide physical IP solutions for optimal performance, power, area and yield. Mr. Brock has served in the IP and EDA industries for over twenty-five years in technical, marketing, management, professional service, and product development at Virtual Silicon, Collett International, Compass Design Automation, Mentor Graphics, and Silicon Compilers. He chaired the Global Semiconductor Alliance's Analogue/Mixed Signal Working Group that produced the AMS/RF SPICE Model, PCM and PDK Checklists used by leading foundries. He holds a BSEE and MBA from Fairleigh Dickinson University.

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