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The MCU guy's guide to FPGAs: The hardware

Posted: 07 May 2015 ?? ?Print Version ?Bookmark and Share

Keywords:microcontroller? MCU? FPGA? multiplexers? digital signal processing?

Another very common type of FPGA implementation technology is based on the use of SRAM configuration cells. Once again, we will consider this in more detail in a future column. All we need to note here is that when the board is first powered-up, the SRAM-based FPGA is loaded with its configuration (we can think of this as programming the device). As part of this configuration, the SRAM cells acting as inputs to the LUT's multiplexers are loaded with the desired 0 and 1 values as illustrated above.

I've not shown the mechanism by which the 0s and 1s are loaded into the SRAM cells because I don't want to confuse the issue. For the purposes of these discussions, we really don't need to worry about how this "magic" takes place. The only thing I will mention here (to give you something to ponder) is that!using a technique called partial reconfiguration!it is possible for one part of the FPGA to instigate the reconfiguration of another part of the FPGA (and vice versa, of course). For those readers coming from a microcontroller and/or software background, we might think of this as being the hardware equivalent of self-modifying code. This means that this technique is very, very powerful, but it comes with the capability to introduce problems that are horrendously difficult to isolate and debug.

General-purpose inputs and outputs

The device will also include general-purpose input/output (GPIO) pins and pads (not shown in the above illustration). By means of its configuration cells, the interconnect inside the device can be programmed such that the primary inputs to the device are connected to the inputs to one or more programmable logic blocks. Also, the outputs from any logic block can be used to drive the inputs to any other logic block and/or the primary outputs from the device. Furthermore, the GPIO pins can be configured to support a wide variety of I/O standards, including voltages, termination impedences, slew rates, and so forth

The very first FPGA was similar to the architecture discussed in this column. Introduced by Xilinx in 1985, the XC2064 (which was created at the 2um technology node) contained an 8 x 8 = 64 array of logic blocks, each containing a 4-input LUT along with some other simple functions. Since that time, FPGAs have evolved dramatically, as we shall see...

More-sophisticated FPGA architectures
As we noted on the previous page, the very first FPGA, the XC2064, which was introduced by Xilinx in 1985, contained an 8 x 8 = 64 array of logic blocks, each boasting a 4-input LUT along with other simple functions. Since they were limited in terms of capacity, early FPGAs were employed only for relatively simple tasks, like gathering glue logic or implementing rudimentary state machines. Over time, however, things began to change...

Year-by-year and node-by-node, the capacity and performance of FPGAs increased while their power consumption decreased. The widespread use of 4-input LUTs persisted until around 2006. In fact, at the time of this writing, the smaller FPGA families still use 4-input LUTs, but higher-end devices may use 6-, 7-, or 8-input LUTs. These big-boys may be used as a single large LUT or split into smaller functions, such as two 4-input LUTs or a 3-input and a 5-input LUT. In a really high-end device, this programmable fabric is capable of representing the equivalent of millions (sometimes tens of millions) of primitive logic gates.

If a logical function!say a counter!is implemented using the FPGA's programmable fabric, that function is said to be "soft." By comparison, if a function is implemented directly in the silicon, it is said to be "hard." (As these functions become larger and more complex, we tend to refer to them as "cores.") The advantage of soft cores is that you can make them do whatever you want. The advantage of hard cores is that they occupy less silicon real estate, have higher performance, and consume less power. The optimal solution is to have a mix of soft cores (implemented in programmable fabric) and hard cores (implemented directly in the silicon). Thus, in addition to their LUT-based programmable fabric, today's FPGAs may be augmented with a variety of hard cores as illustrated below:

Figure 3: A more sophisticated FPGA architecture.

For example, the device might contain thousands of adders, multipliers, and digital signal processing (DSP) functions; megabits of on-chip memory, large numbers of high-speed serial interconnect (SERDES) transceiver blocks, and a host of other functions.

FPGAs with embedded processors
This is where things start to get really exciting... One of the things you can do with the regular programmable fabric in an FPGA is to use a portion of it to implement one or more soft processor cores. And, of course, you can implement processors of different sizes; for example, you might create one or more 8bit processors along with one or more 16bit or 32bit soft processors!all in the same device.

If the FPGA vendor wishes to provide a higher-performance processor that occupies less silicon real estate and consumes less power, the solution is to implement it as a hard core. One very exciting development is the recent introduction of SoC FPGAs by companies like Altera and Xilinx. Consider the Example shown below.

Figure 4: A new class of SoC FPGAs.


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