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The MCU guy's guide to FPGAs: The software

Posted: 08 May 2015 ?? ?Print Version ?Bookmark and Share

Keywords:microcontroller? MCU? FPGA? multiplexers? digital signal processing?

Similarly, in the case of the FPGA flow, we would have to inform the synthesis tool as to the target FPGA (vendor, device family, specific member of that device family, etc.). Also, the synthesis tool outputs an intermediate file that allocates resources like "this function goes into a LUT," but it doesn't actually specify which LUT to use in the FPGA. A variety of techniques, including place-and-route algorithms, are subsequently employed in order to generate the final configuration file.

HDLs versus programming languages
Let's start with the fact that we describe traditional programming languages as being sequential in nature, while we say that HDLs are inherently concurrent, but what does this actually mean? Let's start with a snippet of programming language code as follows:

Figure 2: Pseudo-code example of a programming language.

Note that this is not intended to represent any actual programming language!it's just my own pseudo-language to illustrate the point (this way I cannot be accused of making any mistakes). When a processor executes this program, it does so in a sequential manner. We can think of this as executing one line of source code at a time. We start by declaring two integer variables called intA and intB. At some stage in the program we load an integer value of 3 into intA and a value of 6 into intB.

The next part is the bit we are interested in!the part where we load intA with a copy of the contents of intB, and then we load intB with a copy of the contents of intA. STOP! Did you notice the portion of the previous sentence where I said "...and then we load..."? This is the crucial point. This is where we realise that we are absolutely comfortable with the fact that the conventional programming language is sequential in nature. The result, in this example, is that both intA and intB end up containing a value of 6.

Now let's consider an equivalent example in a pseudo-HDL as shown below. We commence by declaring two 4bit registers. Next, we assign values to these registers. And then... well, what do you think happens next?

Figure 3: Pseudo-code example of an HDL.

The simple answer is that we can visualise both of these statements as being executed concurrently (at the same time), which means that regA ends up containing 6 (the original contents of regB) while regB ends up containing 3 (the original contents of regA).

This is the aspect of HDLs that people with a traditional programming background!like software developers!find it so difficult to wrap their brains around. By comparison, so long as they haven't been "corrupted" by any previous programming experiences, most hardware design engineers instinctively understand the way in which HDLs work, but what do I mean by "work" in this context? Well, read on...

Simulation and synthesis
In the case of a traditional software program, we understand that the program itself is just words and symbols. It doesn't actually do anything until it is compiled into machine code that is run on a processor. So what about our HDL design code? In fact, there are two main things we typically do with our HDL: simulation and synthesis as illustrated below:

Figure 4: Simulation and synthesis.

Let's start with simulation. Our HDL represents the functionality we eventually wish to implement in an FPGA. If we had a real FPGA on a test bench, then!assuming it was already powered-up and loaded with its configuration file!we could apply stimulus signals to its inputs and observe any response signals at its outputs. In the simulation world, we use a testbench to specify the required stimulus and the expected responses, both of which we can store, analyse, and display using a variety of techniques (the above illustration reflects a waveform display on a computer screen).

As an aside, in the case of the early logic simulators, a separate WDL (waveform description language) was used to specify the stimulus and expected response signals. Today, languages like Verilog and VHDL can be used to specify both the design and the testbench, but we digress...

We will return to the logic simulator in a moment, but first let's consider the synthesis part of the picture. The synthesis tool understands what we are trying to "say" with our HDL, so!assuming we're still working with our original example!it will generate a configuration file that will implement something like the following circuit in the FPGA:

Figure 5: Things can happen concurrently in hardware.

Remember that regA and regB are actually 4bit entities!I've just drawn them as shown above for simplicity. Also, I haven't shown any circuitry that would allow us to load values like 3 (binary 0011) and 6 (binary 0110) into these registers. The main thing is to not allow ourselves to become side-tracked by these minor details, but to instead focus on the fact that!in the real (hardware) world!events can indeed happen simultaneously (concurrently). In this case, the internal delays associated with the registers would allow each register to load the value on its input before the value on its output started to change. Thus, following an active edge on the clock signal, each register will end up containing the value that was previously stored in the other register.

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