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The MCU guy's guide to FPGAs: The software

Posted: 08 May 2015 ?? ?Print Version ?Bookmark and Share

Keywords:microcontroller? MCU? FPGA? multiplexers? digital signal processing?

And, just to remind ourselves, a simulator is a program that reads in a Verilog/VHDL source code description and uses this to create a virtual representation of the way in which the hardware would work in the real world. Although the simulator is itself written in a sequential language like C or C++, it's created in such a way as to "fake concurrency" in its sequential world.

The point is that when I see an image like the one below, I think of it in a variety of different ways. For example, I can visualise it as being HDL source code, with a top-level block instantiating sub-blocks (which could themselves instantiate sub-sub-blocks, and so on and so forth). Alternatively, I can visualise it as being a collection of simple integrated circuits containing logic gates and registers (like the old 74-series TTL devices) all mounted on a circuit board. And, of course, I can visualise it as a bunch of functional blocks!each comprising a collection of logic gates and registers!being implemented inside an FPGA.

Figure 10: A hardware design in HDL boasting four blocks (plus a top-level block).

Let's assume that each of our functional blocks contains registers on their outputs, and that all of these registers are driven by a common clock as illustrated above. In this case, we have a classic case of pipelining. The first active clock edge loads whatever value is being presented to the inputs of the device into block bA, after which the inputs to the device may change. The next active clock edge loads the outputs from block bA into block bB and!at the same time!loads the new value being presented to the device's inputs into block bA. The third clock edge loads the outputs from bB into bC, the outputs from bA into bB, and the new inputs to the device into bA!all at the same time. And so it goes. The resulting actions can be visualized as illustrated below:

Figure 11: This hardware example provides a classic case of pipelining.

What this means is that, once the pipeline has been fully "primed" (which occurs on active clock edge #4), every new clock causes the design to load whatever new value is being presented to its inputs and!at the same time C to presents a new value to the outside world on its outputs.

There are two really, REALLY big points to wrap one's brain around here. The first is that only one procedure or function can be active at any particular time in C/C++ (in the ensuing executable machine code, that is); by comparison, all of the functional blocks are going to be active all of the time in Verilog/VHDL (in the ensuing simulation or FPGA implementation, that is).

The second important point is that, although a C/C++ procedure or function can be called multiple times from different places in the main program, that procedure or function still only exists in one place at one time (no, I don't want to ponder the metaphysical aspects of recursion here). For example, consider a software application that calls procedure "pA" from two separate points in the main program as illustrated below:

Figure 12: Calling a procedure from multiple locations in the main software (C/C++) program.

By comparison, if a higher-level block in Verilog/VHDL instantiates multiple instances of a sub-block, then each of those instantiations is an independent "thing" in its own right. For example, consider a top-level block that invokes two instantiations of a sub-block called bA. Four simple scenarios off the top of my head are as illustrated below:

Figure 13: Instantiating a block multiple times in the same hardware (Verilog/VHDL) design.

And just to make sure that there's no confusion (I don't want anyone to think that you can only have multiple instantiations of one type of block), lets ponder one final example showing three instantiations of block bA and two instantiations of block bB as illustrated below:

Figure 13: Instantiating a block multiple times in the same hardware (Verilog/VHDL) design.

Phew! So what do you think? If you are new to Verilog and VHDL and FPGAs, does this clear up any confusion you may have been having? Alternatively, if you are already familiar with HDLs, do you think my comparisons to regular programming languages like C/C++ cover all of the bases, or have I missed anything?

About the author
Clive "Max" Maxfield is the Editorial Director of and the Embedded Systems Conferences (ESC). Max is also editor of the EE Times Programmable Logic and EE Life Designlines. Max is six feet tall, outrageously handsome, English, and proud of it. In addition to being a hero, trendsetter, and leader of fashion, he is widely regarded as an expert in all aspects of electronics (at least by his mother). Max received his BSc in Control Engineering in 1980 from Sheffield Hallam University in Sheffield, UK. He began his career as a designer of central processing units (CPUs) for mainframe computers. Over the years, Max has designed everything from silicon chips to circuit boards, and from brainwave amplifiers to steampunk "Display-O-Meters." He has also been at the forefront of Electronic Design Automation (EDA) for more than 20 years. Max is the author and/or co-author of a number of books, including Designus Maximus Unleashed (banned in Alabama), Bebop to the Boolean Boogie (An Unconventional Guide to Electronics), EDA: Where Electronics Begins, FPGAs: Instant Access, and How Computers Do Math.

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