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Verilog-AMS vs SPICE view for DDR, LCD verification

Posted: 11 May 2015 ?? ?Print Version ?Bookmark and Share

Keywords:IP? SoCs? Analogue Mixed Signal? AMS? simulation?

Here is the third installment of a series covering the pros and cons of using a Verilog-AMS view with respect to a SPICE view for verification of SOC IP having an analogue component. The first article covered power management and mode transition and the second article covered data-converters and clocking.

Analogue mixed-mode simulations (AMS) in an SOC design must be accurate to achieve first pass design success, and hundreds of them may be needed to cover all the process and temperature corners. You can use Verilog/Verilog-AMS, a behavioural abstraction of the circuit that sacrifices accuracy for the sake of run time, or SPICE, which does exactly the opposite. It is thus important to weigh the pros and cons of using a Verilog/Verilog-AMS view with respect to a SPICE view for simulation to achieve the right balance of accuracy and simulation speed, and each analogue block will need its own evaluation. In this paper we comparatively analyse the usage of both the views from the perspective of DDR interfaces, LCD controllers, and on-chip Memories.

DDR sub-system
The DDR sub-system within the SOC is responsible for transferring data between the off-chip DDR memory and the on-chip RAM of the SOC, for the purpose of temporary storage and retrieval during code execution. The DDR sub-system comprises the RAM, the DDR controller, several groups of I/O pads, and finally the off-chip DDR memory itself. The various groups of I/O pads perform different functions, such as data transmission and addressing, performing ZQ calibration, sending out a clock to the DDR memory; sending out control information (RESET, Clock enable), and providing control bits to tell the DDR memory whether to decode the Address bits as row or column addresses.

Figure 1: Top level block diagram showing the components of a DDR sub-sytem as part of SoC.

In any High Speed interface, the important components would be the transceiver, a clock source, a clock recovery circuit, proper pull-ups and pull-downs to define the reset states, and on-die-terminations to ensure proper impedance matching. A DDR sub-system, however, doesn't have a separate analogue PHY. Instead, these functionalities are embedded in the I/O pads themselves. Also a DDR sub-system does not need a clock recovery circuit because the clock needed is sent out separately through dedicated pads.

During the power up phase the DDR memory needs to be kept in the RESET state. When the system is out of RESET then, depending on the use case, the DDR memory must be brought out of its RESET state. But before the DDR memory can be made operational, a routine called 'ZQ calibration' of the DDR pads must be performed. In this routine the strengths of the I/O drivers and the on die terminations are calibrated to make sure that data transfer happens without any corruption.

Figure 2: DDR ZQ calibration routine.

After the ZQ calibration is complete, the controller can enable the clock going out of the chip to DDR memory and de-assert the RESET pin. This step enables the DDR memory for any further data transactions. For reading data from the memory, the read enable is asserted while the address bus carries the address of the memory column/row. This is performed using control pins called CAS (Column Address Select) and the RAS (Row Address Select). To point to a particular location in the memory the row address is latched (Address bus carries row addresses and RAS is high); followed by the latching of the column address (Address bus now carries column addresses and CAS is high).

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