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Manufacturing/Packaging??

Impact of piling on package manufacturing

Posted: 12 May 2015 ?? ?Print Version ?Bookmark and Share

Keywords:flip chip ball grid array? FCBGA? SerDes? thermal interface material? plated-through holes?

Examples of package reliability concerns can include:
???Non-uniform bond-line thickness of the thermal interface material (TIM) applied between the heat spreader and die. Ultimately, this impacts thermal performance in terms of optimal dissipation of heat from the device as warpage can cause strain in the TIM, leading to delamination.
???Bump integrity during temperature cycling from tighter pitch that causes reduced standoff height between the organic passivation material on die to substrate solder mask
???BEOL inter-layer dielectric cracking/delamination

Because of evolving unique package attributes and combinations (figure 3), chip-to-package interaction becomes more of an unknown as HVM packaging solutions from previous silicon nodes become less useful. A systematic and fundamental approach must be carefully delineated to engineer robust BoMs and assembly processes that achieve high margin capability during HVM and customer usage in the field. This will assure satisfactory thermal performance and thermo-mechanical reliability.

Figure 3: "Forces" acting on FCBGA HVM yield.

What do you do?
Gathering empirical data is a necessary requisite. This can be expensive if multiple variables are involved. For any design of experiments, caution should be taken to assure sample sizes provide meaningful statistical confidence. Stress modelling is the most logical mitigating path, but can lead an engineer down a dark labyrinth if not correlated to empirical findings.

Going that extra mile to corroborate suppler material property information can have a significant impact on stress modelling prediction accuracy. A grassroots approach must be established for strong synergy between the silicon and package substrate designer, package development engineer, package supplier, and assembly/test site engineer. Albeit ostensible, these synergetic exchanges should not be underestimated.

Having upfront and thorough discussions with the substrate designer focusing on integration of assembly manufacturing rules during substrate design is a key factor to promoting good assembly yield and reliability. This rudimentary exchange can circumvent substrate design incompatibilities with the assembly process and any untimely misprocess. Understanding supplier capabilities (via roadmaps, manufacturing tolerances, process controls, etc.) and certifying their manufacturing process and internal suppliers (via audit) provide valuable foresight to avoid issues.

Equally important is analysing industry trend data and benchmark common packages that may shed light on HVM yields and package reliability. If you buck the trend, stay abreast of the direction of OEMs and turnkey solutions. Manufacturing process variations such as final package thickness, size, lid alignment, etc., must be taken into account and aligned with the critical specifications.

The key is to run a tight ship where discipline and tightly controlled processes are benchmarks to assembly manufacturing outputs. This not only ensures that you meet final customer needs, but also multi-factory flows such as auto-handling test and inspection equipment. These relationships are imperative to assure FCBGA packaging solutions are compatible with increased functionality in semiconductor devices (figure 4).

Figure 4: Balancing decisions and factors.

Impact of piling functionality
Reliability can be sacrificed if designs get too aggressive. We must focus on an industry trend to design thinner substrates for improved electrical performance. Reducing substrate build-up stacks (i.e., layer count) serves as significant cost savings with respect to overall package cost. However, this cheaper alternative can affect both component and SMT yields, along with board-level reliability (BLR) depending on FCBGA package type (i.e., package-on-package or singulated-based).

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