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Manufacturing/Packaging??

Impact of piling on package manufacturing

Posted: 12 May 2015 ?? ?Print Version ?Bookmark and Share

Keywords:flip chip ball grid array? FCBGA? SerDes? thermal interface material? plated-through holes?

Yields can be further compounded if the substrate material properties (i.e., CTE, Tg, and modulus) are not optimised. Metal balancing and density rules between layers should be carefully enforced and plated-through holes (PTHs) "keep out zones" to avoid design at high stress regions of the package.

Another example of reduced substrate layer count is when signal routing layers change from a robust second metal layer buried by planes of metal buffering stress to the substrate top layer. As a result, routing at the substrate top layer is protected by a weaker organic material like the solder mask, which acts as the last line of defence against displacement stresses generated during temperature cycling. Newton's third law, for every action there is an equal and opposite reaction, is still alive and well. Be prepared!

Takeaway
Like looking both ways before crossing the street or leaving no stone unturned, packaging engineers must make the extra effort to fully comprehend the impact of densifying the package. Weigh the pros and cons. Late in the product development cycle, cost savings can be quickly absorbed by yield loss, re-qualifications, or change to more robust BoMs and/or assembly processes. Co-design teams must establish synergy and focus on the following key areas:
???Optimising material selection and characterisation
???Correlating modelling with empirical results and benchmarking feedback
???Analysing cost sensitive design with yield trade-offs and key manufacturing care-abouts
???Acknowledging and creating an early action plan to address the inherent variances in materials, assembly and test

If the pros and cons are under-scoped, like blindly crossing a busy street, the packaging engineer will be overcome by yield challenges or even worse, lost credibility.

Reference
International Technology Roadmap for Semiconductors, Assembly and Packaging, 2012 Tables, Package Warpage at Peak Processing Temperature

About the authors
Jaimal Williamson is responsible for development and qualification of Embedding Processing FCBGA devices within Texas Instruments' Worldwide Semiconductor Packaging group. Jaimal received a BS in Chemistry from Grambling State University and an MS in Polymers from the Georgia Institute of Technology. Jaimal has one issued patent and four pending patent applications, and has also co-authored two papers related to microelectronic packaging technology.

Leon Stiborek is a senior IC Packaging engineer with over 25 years of commercial and government electronic packaging development and manufacturing experience. Currently he is involved in Silicon to Package readiness development and package failure assessments.


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