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Connecting passive components to logic gates

Posted: 14 May 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Digital gates? transistors? CMOS? PWM? voltage-controlled oscillator?

The logic edges at the XOR output ring the LC tank, which is tuned to resonate at the desired harmonic frequency. Odd harmonics are available when the XOR output is a symmetrical 50 per cent duty cycle, even harmonics can be picked off with a delay line that sets the XOR output pulse duty cycle to maximise the desired harmonic. The amplifier restores the LC tank ringing to digital logic levels.

Phase detectors, line drivers, and pulse shapers
There are instances when we really want the phase relationship between the reference and the VCO (voltage-controlled oscillator) to be tightly controlled. In this situation, the XOR phase detector shown in figure 2 doesn't quite cut it. An example is when the reference is a random NRZ (non-return-to-zero) data stream, and we want to phase-lock a VCO to generate a recovered clock such that the rising clock edges occur at the very centre of the data eye pattern seen on an oscilloscope.

Since the data transitions of a weak signal get "jittery" in time due to thermal noise (among other causes) in the receiver, the best time to sample the data as to being a one or a zero is at the time farthest away from the transitionsi.e., the eye centre at the amplitude peaks of the analogue modulation waveform.

Figure 4: A D-type flip-flop and a VCO lets you set a sampling point in the centre of a signal eye diagram.

Here, the incoming data stream clocks the D-type flip-flop, sampling at that instant whether the VCO clock is high or low. (Only the rising data edges do the clocking; an XOR with a delayed input could allow clocking on both rising/falling data edges but not necessary.) The averaged DC output feeds back to the VCO to servo it to where the VCO falling clock edge seeks out the data transitions. Thus, the rising clock edge that actually samples the data bit is in the eye centre where it belongs. This requires a 50 per cent duty clock, which can easily be obtained by using a VCO at twice the desired frequency and dividing by two.

Where long runs of consecutive 1s and 0s are present in the data stream, a timed tri-state pump-up or pump-down pulse would be preferable unless the RC time constant is made very long relative to the run of consecutive bits.

This is the only use of digital logic that I know of that tolerates a D flip-flop seeking out its own point of metastability, but it doesn't matter; the occasional metastable result is but a drop in the bucket during integration of thousands of pulses by the RC filter.

Of course, the D flip-flop must be chosen for fast setup/hold times relative to the data bit rate, and there will be some drift with temperature and power supply variations through the setup/hold specs. "Infinite gain" is a bit of a misnomer; it refers to the fact that a D flip-flop, when operated in violation of setup/hold times, will either go high, low, or oscillate as a result of extremely small changes in its data/clock timing violations. Strange, but it does work.

The last time I used this technique was with a 74AHC74 D flip-flop as the phase detector. The resulting digital output looked something like the bottom waveform of figure 4. I might have been able to remove the back-and-forth frequency fluctuations with more attention to the RC filter parameters, but the boss was a-chomping at the bit to move on to the next crisis and the loop worked well enough for our purposes.

Another use for complementary digital outputs is as a push-pull (yeah, I know, a very retro term) transformer driver (figure 5).

Figure 5: Transformers turn logic gates into live drivers.

VCC/2 at the centre tap lets the voltage induced on the logic high side (due to the pulldown on the logic low side) from becoming diode clamped to VCC with some logic families. I've used this technique with 74S series TTL with the centre tap at VCC and got away with it on a prototype, but would not recommend this for a production design. Never tried this with 74(A)HC, only ECL and 74S TTL. With the stronger source drive of AHC the centre tap might not be needed.

So far, all these passive components have been applied to the gate outputs. Here are some neat things that can be done at gate inputs, assuming they are Schmitt-trigger gates (figure 6).

Figure 6: Use Schmitt-trigger XOR, OR, or AND gates to make pulse shapers.

Driving a resonant LC tank circuit
Now we'll have a look at the neat things that you can do by driving a resonant LC tank circuit from a logic gate. Figure 3 touched on this. Now, let's have a peek at a bit more detail. Figure 7 shows the circuit.

Figure 7: A series of logic edges at a sub-harmonic of the tank resonant frequency will cause it to ring.

Figure 8 shows the response of a tank tuned to 156.2kHz to a single rising edge.

Figure 8: A single blue edge twangs the yellow tank like a guitar string. (Note all of the following figures have the colours swapped.)


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