Connecting passive components to logic gates
Keywords:Digital gates? transistors? CMOS? PWM? voltage-controlled oscillator?
And so on. As long as the alternating digital edges can be made to fall on the alternating peaks of the resulting sine wave, the tank will ring. To put it another way, the timing between alternating digital edges must equal an integral number of half-periods of the desired harmonic.
Driving pulse length
Previously we found that the duty cycle on a driving square wave affects the relationship between its rising and falling edges and the peaks of the tank circuit (figure 7). Creating the required pulse lengths is, however, another story. This is usually not done digitally; that would require the same high-frequency clock we are trying to recreate!
Perhaps a very-high-frequency clock and counter chain could be triggered from the low-frequency edge we want to multiply and synthesise the desired pulses. But there are analogue methods (as discussed earlier) using monostable multi-vibrators, RC networks with gates, and delay lines using readily available lumped LC with logic gates devices or actual terminated transmission line for the higher frequencies. It is even possible to get double the use out of a length of transmission line by not terminating it, and using the round-trip time of the reflected pulse as the timing element, but this can get tricky.
Now we come to an interesting case where the driving pulse is a half-cycle or less of the sine wave. Because of the limitations of the function generator I had to lower the tank resonant frequency to get the desired duty cycle. The tank circuit used to generate the waveforms in figure 13 uses a 1?H inductor (Q unknown, is actually a very small RF choke from the junk box) in parallel with a 100nF capacitor, and the coupling capacitor to the digital drive had to be increased to 270pF. The resonant frequency of the new tank is about 500kHz. The function generator output is now the main (not TTL) output with reduced rise time since the faster TTL edges excited a parasitic ringingpossibly the self-resonance of the RF choke.
Figure 13: The 50% duty cycle edges line up with every sine wave peak, and the pulse edges straddle the sine zero crossing. |
So what's the point of turning a square wave into a sine wave of the same frequency? Among other things, you can remove high frequency jitter outside of the tank bandwidth (the higher the Q, the better), especially when recovering a bit clock from a noisy serial bit stream:
Figure 14: At 20% duty cycle the pulse edges still straddle the sine zero crossing. In this situation the pulse width itself is not overly critical; sloppy timing methods (within reason) to create the pulse width are acceptable. |
Figure 15 shows a square wave driving the XOR to drive the tank with a narrow pulse (as in figure 14) at every rising and falling edge, but it could just as easily be a densely-coded serial bit stream such as biphase or Manchester where there are always either one or two edges per bit. Each edge rings the tank tuned to double the bit rate; a simple divide-by-two is all it takes to recover the serial bit clock. Even at minimum transition density of one edge per bit, the tank rings to fill in the missing edges and keep the recovered clock going. I've used this clock recovery method at 250 Mbit/s on 4b5b encoded serial data.
Figure 15: An XOR Schmitt trigger easily creates the sloppy pulses of Figure 3 with a simple RC network. |
This can be much cheaper than a PLL (phase-locked loop) with a VCXO (voltage-controlled crystal oscillator), as long as you don't mind the fact that the tank initially needs to be tweaked into tune. It takes about the same effort as tuning one-sixth of a guitar.
Other uses for digital logic tanks include variable phase shifting, automatic phase correction of a serial bit stream sample clock, frequency translation, packet clock start-up, and clock synthesis through frequency addition and subtraction (heterodyning) using an XOR gate as a frequency mixer.
About the author
Glen Chenier is an analogue engineer.
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