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Enhancing analogue design verification using UVM

Posted: 15 May 2015 ?? ?Print Version ?Bookmark and Share

Keywords:system on chip? analogue and mixed-signal? AMS? Universal Verification Methodology? UVM?

As technology becomes more integrated into our everyday life, our chips need to better communicate with the analogue world. Most modern system on chip (SoC) designs therefore contain analogue and mixed-signal (AMS) elements integrated with digital components. According to Sandip Ray of Intel, AMS elements currently consume about 40% of the design effort, and an estimated 50% of errors in recent chips that require a redesign are due to bugs in the AMS portion of the design [reference].

This increase in AMS content in silicon creates several verification challenges: how do we verify the analogue design itself, its integration with the digital, and whether the combination achieves the intended overall function? However, there is no standard or even widely adopted approach to this despite the continuous increase in analogue content. One potential route is via an efficient, reusable AMS verification approach using the Universal Verification Methodology (UVM) outlined below:

To demonstrate this approach, let's use the AMS design shown in figure 1. This is a very simplified version of a power management design where the LDO output voltage is a function of the control signals from the digital sub-chip, the bias currents from the bias generator, and the reference voltage.

Figure 1: A simple power management AMS design.

This approach to verification is multi-layered:

1. We must verify the analogue IP design itself using traditional SPICE simulations

2. We must verify the integration of the analogue with the digital:
i) At block level
ii) And at SoC level
Regarding point 2 above, the first major consideration is the speed of simulation. SPICE simulations are notoriously slow (even on the lowest accuracy) and so many engineers develop a model of the analogue block to enable faster simulation speeds. The model will often use real numbers or electrical signals. However, this creates a third verification task:

3. Verification of the accuracy of the model

In this outline I will focus on point 2 above and we will consider how to do this using a constrained random approach based on UVM. An outline of a UVM test bench is shown in figure 2.

Figure 2: UVM test bench.


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