Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > T&M

Testing SATA DevSleep for SSDs

Posted: 22 May 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Intel? DevSleep? SATA 3.2? solid-state drives? SSD?

Additional tests under consideration include checking coherency after entering and exiting DevSleep from a reduced power state. Here devices will be interrogated to verify they support the DEVSLEEP_TO_REDUCEDPWRSTATE capability within their Identify Device data log. If this bit is set to one, devices are required to exit DevSleep and return directly to slumber or partial if they initially transitioned from one of these low power states.

Measuring actual power draw
While the goal of DevSleep is to save power, the SATA specifications do not define the amount of power that should be reduced while in DevSleep. While this is considered a vendor specified parameter, developers implementing DevSleep will clearly benefit from optimising their devices power profile during DevSleep. Multimeters are one option for tracking power consumption for peripheral components. With the growing focus on battery life, some bus analysers now incorporate power analysis measurements that are synchronised with protocol level traffic. This makes it possible to correlate the device's power usage at the precise point where commands are issued or state transitions occured. The SATA specification does not mandate specific power levels for DevSleep devices. Howerer this option to observe power at both the source and the sink during Dev Sleep testing can be helpful for profiling actual power behaviour.

Power analysis is also useful when testing SSDs during normal operating mode because it can be used to identify when devices are performing block reclamation. Also known as "garbage collection", SSD's must periodically relocate valid data and then erase blocks before writing new data. This normally occurs during idle time but can contribute to latency if the SATA controller must wait for garbage collection to complete. Power analyisis tools will often show a spike in power consumption during garbage collection. This is one of the few empirical ways to identify when background reclamation is occuring. Figure 5 illustrates how power analysis tools can be used to identify a spike in power draw. This can be attributed to additional circuitry internal to the device that is actively relocating partially written blocks.

Figure 5: A spike in power consumption is one of the few empirical ways to identify when "garbage collection" occurs within SATA SSDs.

The ability to unambigously test DevSleep operation and measure the correpsonding power savings at the SSD interface gives developers the confidence that they are optimising the power profile while providing the best user experience for mobile systems.

About the author
Mike Micheletti contributed this article.

?First Page?Previous Page 1???2???3???4

Article Comments - Testing SATA DevSleep for SSDs
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top