Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Manufacturing/Packaging
?
?
Manufacturing/Packaging??

A closer look at Samsung's 14nm node

Posted: 14 May 2015 ?? ?Print Version ?Bookmark and Share

Keywords:14nm? process nodes? HKMG? gate-first? CMOS?

Samsung has done a good job shrinking the lag for its 14nm to about six months, keeping Intel at bay in the release of process nodes.

Nearly a decade ago, the future appeared to be a divide between gate-last and gate-first high-k metal gate (HKMG) transistors that were soon to be implemented in the 45nm or 32nm process nodes. Intel went with a gate-last process while the IBM Common Platform, which included Samsung, adopted a gate-first process.

The gate-first approach follows a traditional CMOS process where the gate stack is deposited and patterned before the formation of the source/drain implants. The process is somewhat more complicated in that the oxide or nitrided gate oxide is replaced with a high-k gate dielectric (for example HfO2/oxide stack) plus a thin work function (WF) metal layer is formed on top of the high-k gate dielectric. A polycide gate layer covers the work function metal to complete the gate stack.

Both the gate-first and gate-last processes require a dual-work function metallisation scheme to separately tune the NMOS and PMOS transistor threshold voltages. This complicated the fabrication process for making metal gate transistors as several metal deposition and etch processes are required to form the two work function metals and the remaining gate fill.

Several arguments were made for the gate-first process including the ease of migration from the familiar poly gate process, to fewer restrictive design rules. For example, the gate-first process permits gate strapping and perpendicular gate wiring (Figure 1, left). The gate-first process was initially developed by Sematech and the IBM Fishkill Alliance that included Samsung.

Intel adopted a gate-last process for their 45nm node and this placed additional layout restrictions for the transistors. One of which was the requirement for the gates to all lie in the same direction (Figure 1, right). The gate straps are implemented here in a metal contact level.

Plan View

Figure 1: Plan View SEM Image of Samsung 32nm Gate Layout (left) and Intel 45nm (right)

Samsung's 32nm HKMG NMOS and PMOS transistors are shown in Figure 2. The NMOS and PMOS transistor stacks comprise an HfO2/oxide gate dielectric, a TiN metal cap, the dual work function metallisation (NMOS or PMOS) and finally a nickel silicided polysilicon top-layer.

The HfO2/oxide gate dielectric stack is common to nearly all HKMG transistors including those fabricated by Intel, TSMC, GlobalFoundries and Samsung. The oxide layer is several monolayers thick and is likely formed by thermal oxidation of the silicon substrate. This thermal oxidation creates a pristine oxide/silicon interface, free of carrier traps or surface states. The HfO2 high-k gate dielectric would be formed by atomic layer deposition (ALD), as is the TiN cap layer. The TiN is used to protect the HfO2 during later processing.

The dual work function metallisation used by Samsung is visible in Figure 2, where a single work function metal is seen on the NMOS transistors and two are seen on the PMOS transistors. The presence of the two WF metals on the PMOS transistor indicates that the PMOS work function metal was deposited first, while the NMOS transistors where masked, followed by the deposition of the NMOS work function metal.

The sides of the polycide gate, the work function metals and gate dielectric are nearly coplanar, indicating that all three were patterned and etched together after their deposition.

Samsung 32 NMOS transfer

Figure 2: Samsung 32nm NMOS transistor (left) and PMOS transistor (right)

Samsung kept the gate-first process for its 28nm node, and then switched to a gate-last HKMG process for its 20nm node Exynos 5430 octa-core SoC. The key difference between the gate-first and gate-last process is when the metal gates are formed. Whereas the gate-first process has its gate structure fabricated before its source/drain regions, the gate-last process forms the gate after the source/drains. This is done by double-patterning a sacrificial gate layer (typically polysilicon) to form the long parallel sacrificial gate lines. A third pattern is used to cut the long lines into the gate segments as shown in Figure 3. After processing the source/drain regions, the sacrificial gates are removed, followed by the deposition of the gate dielectric and gate metallisation.

Samsung 20nm

Figure 3: Samsung 20nm gate layout

Like Intel's 45nm process, Samsung's 32nm gates are unidirectional, and gate strapping is done with a metal 0 interconnect.


1???2???3?Next Page?Last Page



Article Comments - A closer look at Samsung's 14nm node
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top