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Envisioning better protocol debug

Posted: 29 May 2015 ?? ?Print Version ?Bookmark and Share

Keywords:debug? verification? IP? embedded software? SoC?

The new app features a lab-equipment style viewa user interface with which verification engineers are familiar. It's essentially the same view an engineer would have if he or she hooked up the real device to a piece of lab equipment. This gives them better visibility into design behaviour as it "speaks the language" of the specifications.

The app's channel view abstracts the communications between the VIP and whatever it's talking to (in the above example it's a disc drive) as commands that are found in the USB specs. Rather than describing the results at the RTL chip-level details, this feature offers a higher-level view of how the communications are conforming to the particular interface specification. Therefore, it's easier to see whether the sequence of commands and responses is correct. A state machine view is also provided that shows what state the VIP is in and how it got there. No longer does the verification engineer have to extrapolate between his observations about what the design is doing and what the interface spec says it should be doing.

And in this way, you can see where your design may have a bug with respect to implementing the specification.

So, with this app introduction, one of the churning wheels of debug technology has caught up with a key design verification challenge and promises to take a big bite out of debug as a percentage of verification time.

About the author
Brian Fuller, a former editor-in-chief of EE Times, is now editor-in-chief with Cadence in San Jose.

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