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36Mb synchronous SRAMs flaunt on-chip error-correcting code

Posted: 28 May 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Cypress Semiconductor? SRAM? ECC? military? data processing?

Cypress Semiconductor Corp. has unleashed what it touts as the industry's highest-density synchronous SRAMs with on-chip error-correcting code (ECC). According to the company, the integrated ECC feature enables the 36Mb synchronous SRAMs to deliver the highest levels of data reliability, simplifying designs for various military, communication and data processing applications.

Soft errors caused by background radiation can corrupt memory content, resulting in a loss of critical data, stated the company. A hardware ECC block in Cypress' synchronous SRAMs performs all error correction functions inline, without user intervention, delivering best-in-class soft error rate (SER) performance, the company claimed. The devices are pin-compatible with current synchronous SRAMs, enabling customers to enhance SER and system reliability while retaining board layout. Additionally, the SRAMs promise to help reduce power consumption by as much as 36 per cent over competing solutions.

The 36Mb synchronous SRAMs are available in industrial temperature grade in RoHS-compliant 100-pin TQFP and 165-ball BGA packages.

Cypress plans to expand the family of high-performance synchronous SRAMs with ECC with additional densities this year.





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