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Employing deep wells in analogue IC design

Posted: 05 Jun 2015 ?? ?Print Version ?Bookmark and Share

Keywords:CMOS? NMOS? ADC? ground? noise?

On a conventional CMOS process (figure 1), NMOS devices are formed in a P well or substrate connected to ground (or the most negative supply in the circuit). PMOS devices are formed in an N well connected to the most positive supply.

Substrate noise caused by minority carrier injection into the substrate and well can be collected by the use of well taps and/or guard rings. An additional problem exists in that capacitive coupling of noise from the well to the substrate means that more noise reaches the supply. In digital circuitry this is usually not a problem owing to the relatively high noise immunity of logic gates. However in analogue design, for example a 12bit ADC, noise can be a serious problem. A variety of techniques can be used to minimise this noise, for example by keeping analogue devices surrounded by guard rings, or using a separate supply for the substrate/well taps. However guard rings alone cannot prevent noise coupling deep in the substrate, only surface currents.

Another problem is that it is not possible to isolate NMOS devices. So relatively noisy digital logic cannot be isolated completely from more sensitive analogue areas.

Figure 1: A typical CMOS inverter shown in cross section. Substrate noise currents are shown as red lines.

A solution is to isolate the NMOS devices by using an extra well C a deep N well. So in figure 2 the NMOS device is fabricated in a P well or substrate completely surrounded by an N-type diffusion.

Figure 2: A deep N well CMOS inverter shown in cross section. Substrate noise currents are shown as red lines.

In this case, the deep N well is formed by a high-energy ion implantation to give peak impurity concentration deep enough to un-affect the NMOS device performance. Connection to the deep N well is formed by a N well ring that is connected to VDD. The deep N well has the effect of decreasing the noise coupling through it to the substrate and giving the advantage of fully isolated NMOS devices C which can in theory be at a different potential from ground.

The implications on layout are of course larger area for nmos devices due to the extra N well rings used to connect to the deep N well. However the noise performance improvements justify this for sensitive analogue design.

In summary, the use of deep N well devices can significantly reduce noise coupling between sensitive analogue areas and more noisy digital regions in mixed-signal designs.

About the author
Keith Sabine, product manager for analogue solutions at Pulsic Ltd. (Bristol, England), has 35 years of experience in the semiconductor and EDA industries, starting out as a bipolar designer at Fairchild Semiconductor before moving into CMOS process development and characterisation at Plessey Semiconductors. His EDA career has included time at Cadence, Simplex, Apache, and now Pulsic.

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