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AMD reveals power capabilities of Carrizo

Posted: 04 Jun 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Advanced Micro Devices? notebook? processor? FinFET? Intel?

Advanced Micro Devices has unveiled the specifics of its latest x86 processor, Carrizo, emphasising the chip's single, scalable architecture and video processing capabilities for notebooks. The company disclosed some of its engineering secrets for squeezing out more performance at lower power budget.

While made in a 28nm process, AMD hopes Carrizo and the lower-tier Carrizo-L will sport power and performance advantages for mainstream notebooks compared with Intel's 14nm FinFET Broadwell chip. Carrizo is made with four AMD Excavator x86 cores and eight GPUs using AMD's Graphics Core Next architecture, while being 30 per cent more power efficient than the previous generation Kaveri chip, stated the company.

"We didn't have new process technology node to work with on this design. We had to come up with a compelling design in the existing Kaveri technology," said Sam Naffziger, an AMD corporate fellow and the company's lead engineer on power issues. AMD has reduced typical power two fold generation-over-generation while improving performance-per-watt by 2.4x in Carrizo, Naffziger added.

AMD is gunning for a 25x improvement in energy efficiency in performance-per-watt by 2020 and expects to save system level power in Carrizo by integrating its south bridge I/O unit into the die. Carrizo is 29 per cent denser than its predecessor and has a smaller footprint, allowing for quicker cooling, less leakage, and less power consumption overall. The result is additional thermal headroom that allows AMD to increase voltage if necessary.

Carrizo block diagram

Carrizo block diagram. Source: AMD

AMD made many architecture-level changes to improve power and boost instructions per clock, including doubling the cache to 2MB. The L1 cache is a known bottleneck to performance, Naffziger said. Doubling the cache also saves power by not forcing the processor to go to higher levels of cache or DRAM.

Although AMD announced a high bandwidth memory (HBM) DRAM stack for high-end computers, the company wouldn't comment on plans for integrating HBM into future notebook chips. An AMD spokesman said it would be fair to assume HBM would eventually make it to the notebook roadmap.

Engineers created thermal-aware floorplans and voltage islands so Carrizo's Excavator cores are separated from power-hungry memory interfaces. "Things that can generate heat were separated on the die so they can run at higher power levels and generate performance," an AMD spokesman said.

"When we want graphics to go fast we're increasing voltage everywhere with an increase in active power and leakage," said Joe Macri, a CTO at AMD. "What we've been able to do by putting the graphics engine on its own voltage plane is we can turn on more of it when we're at lower power. Increased voltage islands have much more independent control," he added.

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