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Realising true FPGA-based verification

Posted: 11 Jun 2015 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? verification? EDA? simulations? emulation?

As more tested block-level RTL rolls off the verification conveyor belt, it can be assembled into sub-systems, obviously requiring a greater capacity platform, shown here as the HES-7 with Xilinx UltraScale. Another benefit of this scalability is that such platforms are also a cost-effective substitute for big-box emulators for the purpose of regression testing, where the critical factor is raw speed. FPGA-based verification is well known to provide far superior MHz-per-cent throughput than big-box emulation, so banks of FPGA-based platforms of this type are often assembled into a cost-effective regression farm.

Figure: Scalability allows reuse of FPGA platforms at different project stages.

As we progress to the full system, these already-impressive platforms may be assembled into high-speed backplanes; in some cases, these can be linked together into systems modelling RTL into the multi-billion-gate scale. Throughout this vast increase in scale, the scalability of HES-7 hardware options and the consistent integration provided by HES-DVM allows verification teams to make most efficient use of the project's resources.

Meanwhile, as the RTL is maturing, the software team has been using a virtual environment modelled at the transaction level, probably employing OSCI SystemC or a similar high-level methodology. There are additional opportunities for a hybrid approach between the software and hardware flows; that is, between the virtual model and the verification environment. This might happen with or without the FPGA hardware, or perhaps it might directly link the Virtual Models and the FPGA hardware, bypassing the RTL simulator entirely. These hybrid approaches are becoming more popular within SoC teams, but they are a subject for another article (keep watching this space).

The above diagram then brings us to the familiar ground of system integration, where the RTL is fully available but the SC device is still months away. It is at this time that the software team greatly benefits from having multiple copies of the SoC design modelled fully in the FPGAs, and running at the high speed that only FPGA-based prototypes can supply. Perhaps some teams need only part of the SoC design, in which case, the FPGA platforms may be re-employed as stand-alone in-system test rigs for the software developers. Again, the secret sauce of this whole approach is scale and scalability.

Welcome to a new era of FPGA-based verification
As we have discussed, FPGAs are an extremely flexible platform for the verification of SoC designs, at all levels of the design, and at all staged of the project.

As SoC designs have grown in size and complexity, the need for simulation acceleration and FPGA-based prototypes has kept pace only by employing the very largest and most advanced FPGA technologies. Alongside this growth, advances in transactors and verification environments, such as UVM, have made it not only possible, but also necessary, to fully integrate simulation and FPGA hardware. This need for scale and scalability has led us from FPGAs being used mainly for prototyping to this new era of FPGA-based verification.

About the author
Doug Amos is a one-man-army FPGA consultant. Doug has carved out a living from programmable logic and FPGAs for over 30 years, holding technical positions with Altera, Synplicity, and Synopsys. He did his first programmable logic design in the mid-80's, and was a freelance consultant designer and "PIP-Pilot" back when LUTs were still a pretty neat idea. Since then, Doug has designed or supported countless FPGA and ASIC designs, either as an independent consultant or working with the leading vendors.Doug became Synplicity's first engineer and Technical Director in Europe, and has presented widely on FPGA design and FPGA-based prototyping, including lead-authoring the FPGA-based prototyping Methodology Manual in 2011.Doug holds an honours degree in Electrical and Electronic engineering from the University of Bath, England.


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