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The MCU guy's guide to FPGAs: Configuration

Posted: 15 Jun 2015 ?? ?Print Version ?Bookmark and Share

Keywords:MCU? FPGA? programmable logic? one-time programmable? antifuse?

This is the third instalment in our quest to introduce MCU guys and gals to the wonderful world of FPGAs (see also The MCU guy's guide to FPGAs: The hardware and The MCU guy's guide to FPGAs: The software).

As usual, before we plunge headfirst into the fray with gusto and abandon, it's probably a good idea to remind ourselves of some fundamental factoids so as to ensure that we're all tap-dancing to the same drum beat with regard to basic FPGA concepts (and I know whereof I speak, because my dear old dad used to be a tap-dancer on the variety hall stage as a young man).

As we discussed in the "Hardware" column, the primary programmable fabric inside an FPGA comprises "islands" of programmable logic blocks basking in a "sea" of programmable interconnect. The device will also include general-purpose input/output (GPIO) pins and pads, which are not shown in figure 1.

Figure 1: Inside an FPGA.

The FPGA also contains a bunch of configuration cellsmillions of the little rascals in the case of the larger devices. These configuration cells are used to perform a variety of tasks. Some will be used to define the contents of the lookup tables (LUTs). Others will be used to make or break connections between different sections of interconnect, thereby connecting the various entities within the device, including connecting the primary general-purpose input/output (GPIO) pins to the internal functional elements. Furthermore, the GPIO pins can be configured to support a wide variety of I/O standards, including voltages, termination impedances, slew rates, and so forth.

Alternative configuration cell technologies
There are three main technologies that are commonly used to implement the configuration cells inside an FPGA: antifuse, Flash, and SRAM-based.

Let's start with antifuses, which have historically been of interest for high-radiation environments like aerospace applications. Antifuse-based devices are programmed off-line using a special device programmer. These devices are non-volatile (their configuration data remains when the system is powered down) and their function is immediately available to the system when it first powers up. However, this is a one-time programmable (OTP) technology, which means that once you've programmed a device there's no going back.

Flash-based FPGAs may be programmed off-line or while resident on the circuit board. Like antifuse -based devices, the Flash configuration cells are non-volatile; unlike antifuse-based devices, the Flash configuration cells are multi-time programmable (MTP) and can be re-programmed with a new configuration if required. In some cases, the Flash is large enough to hold two or more configurations. This means that the device can be running using one configuration while a second configuration is loaded into another area of the Flash. Once the new configuration has been successfully loaded and verified, the device can be instructed to switch over. This is very useful with regard to tasks like performing secure remote upgrades.

Both antifuse and Flash-based FPGAs have the advantage of low power consumption. However, both technologies require additional processing steps on top of the basic CMOS process used to create silicon chips, resulting in the fact that they are typically one or two generations behind the leading-edge fabrication technology.

In the case of SRAM-based FPGAs, each configuration bit has an associated SRAM cell. One advantage is that these devices can be created using the latest-and-greatest CMOS technology without requiring any additional process steps. One disadvantage is that they are volatile, which means their configuration is lost whenever power is removed from the system. This also means that SRAM-based FPGAs have to have their configuration reloaded every time the system is powered up.

Historically, SRAM-based FPGAs were not considered to be suitable for high-radiation environments. More recently, however, new techniques have come into play, like using triple modular redundancy (TMR), which involves replicating the design three times inside the device. When combined with having the FPGA constantly perform CRC checks on its configuration bits and reloading any portion of the device that becomes corrupted, this approach has proved to be so successful that multiple SRAM-based FPGAs are on the Curiosity Rover, which is currently trundling around Mars (the rover also contains a bunch of antifuse-based FPGAs).

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