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The MCU guy's guide to FPGAs: Configuration

Posted: 15 Jun 2015 ?? ?Print Version ?Bookmark and Share

Keywords:MCU? FPGA? programmable logic? one-time programmable? antifuse?

Last, but not least, some FPGAs use a hybrid approach that involves a mix of Flash and SRAM configuration cells. On power-up, the contents of the Flash are copied over into the SRAM-based configuration cells in a massively parallel fashion. Later, a new configuration can be loaded into the Flash while the FPGA keeps running using the old configuration stored in its SRAM.

For the remainder of this column, we will focus on SRAM-based FPGAs, because (a) these account for the vast majority of devices and (b) they offer some very interesting capabilities like dynamic partial reconfiguration. Furthermore, we will use Xilinx FPGAs as the basis for our discussions (Hey, I had to pick someone LOL).

SRAM-based FPGA configuration modes
SRAM-based FPGAs come equipped with a small group of "configuration mode" pins. As illustrated in the following image, these pins are typically hard-wired to logic 0 and 1 values, which are used to inform the FPGA which configuration mode it is to use.

Figure 2: Basic configuration modes.

The simplest technique is to perform a serial load with the FPGA as the "master" device. In this case, the configuration file is typically stored in an external serial Flash memory device. When the board is powered up, the FPGA initiates and controls the loading of the configuration bitstream from the Flash memory.

Figure 3: Serial load with the FPGA as the master.

Observe the "configuration data out" signal coming out of the FPGA. One use for this signal is to read the configuration data back out of the device. Another possibility is for multiple FPGAs to be daisy-chained together and to share a single external configuration memory device as illustrated in figure 4.

Figure 4: Serial load with the FPGA as the master.

The advantages of the serial load with the FPGA as the master device mode are that the Flash memory device is inexpensive, this mode uses very few pins on the FPGA, and it requires very few tracks on the circuit board. The disadvantage is that it's a relatively slow technique in the scheme of things.

As opposed to using a serial load with the FPGA as the master device mode, we can use a parallel version. Using a multi-bit bus dramatically speeds the configuration process, but it does consume more pins on the FPGA and it requires more tracks on the circuit board.

Thus far we've only considered the FPGA to be the "master"it's also possible for it to act as the "slave." Consider a circuit board containing both a microcontroller and an FPGA, for example. In this case, the designers may decide to use the microprocessor to load the configuration bitstream into the FPGA. This scenario conveys a number of advantages, not the least being that the microcontroller might be used to query the environment in which the system resides, and to then select alternative configuration bitstreams to be loaded into the FPGA accordingly.

Note that, in the case of an SoC FPGA like a Zynq device from Xilinx that contains a hard multi-core microcontroller sub-system, this processor normally controls the loading of the configuration bitstream that is used to program the traditional FPGA fabric.

The last of the traditional configuration options is to use the FPGA's JTAG port. One advantage of this approach is that it doesn't consume any of the FPGA's general-purpose input/output (GPIO) pins; one disadvantage is that it's not the fastest way to load an FPGA. As usual, I could waffle on about different aspects of the JTAG approach for ages, but that's probably a topic for another day.

Introducing the Configuration Engine
One more topic I want to mention here is that of the Configuration Engine. This is a small function that is implemented as a hard core on the FPGA as illustrated below.

Figure 5: Serial load with the FPGA as the master.

The Configuration Engine is a hard core function in the FPGA.

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