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10nm node offers lower gate costs

Posted: 16 Jun 2015 ?? ?Print Version ?Bookmark and Share

Keywords:10nm? 20nm? CMOS? FinFET?

The 10nm node opens a window of opportunity to secure some benefits from technology scaling even as supply chain logistics for semiconductors continues to face increasing challenges.

In March 2012, International Business Strategies (IBS) projected that gate costs at 20nm and 16/14nm would be higher than previous generations of technology. The analysis of the gate cost for 10nm now exhibits a different pattern, shown in the figure below.

While IBS did not project that scaling would stop, it predicted that cost penalties will occur with the adoption of 20nm bulk CMOS HKMG and 16/14nm FinFETs. These predictions on gate cost have been shown to be correct, and while 20nm products are in high volume for Apple, wafer capacity at 20nm is much lower than at 28nm.


After two nodes of increases, gates prices are expected to decline at 10nm.

TSMC provides another example. Its wafer capacity at 28nm is 150,000 wafers per month (WPM), but its wafer capacity at 20nm is nearly a third as much60,000 WPM. Globalfoundries also has 20nm capacity in its Malta, New York fab, but the primary emphasis of this facility is on FinFETs. As for Samsung Electronics and UMC, they have decided to bypass 20nm.

While 16/14nm wafer volumes are ramping, wafer capacity at 16/14nm is again lower than 28nm. The wafer volume at 16/14nm is also driven by Apple again, but the length of use for 16/14nm technology will be determined by how rapidly 10nm will occur.

The lower gate cost at 10nm is due to the higher gate density that can be obtained compared to the increase in wafer cost. To attain lower gate cost at 10nm, there will be the need for high systemic and parametric yields, but this is achievable.

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