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What's inside 1Xnm planar NAND?

Posted: 23 Jun 2015 ?? ?Print Version ?Bookmark and Share

Keywords:NAND? 1Xnm? flash memory?

Makers of NAND flash are now selling their 1Xnm class of planar flash memory, which could possibly not make it past 10nm node. Even so, here's an analysis of 15/16nm by TechInsights.

Over the last year and a half, the major NAND flash makers have started selling their 1Xnm class of planar flash memory. According to our sourcing of the devices on the open market, summarised in Table 1, Micron was first with product appearing in February of 2014, followed by SK-Hynix in October. Nearly six months later, products sporting Samsung 16nm or Toshiba 15nm NAND flash showed up in our laboratories.

There has been much discussion in the literature on the end of lithographic scaling of planar NAND flash, and its replacement with vertically stacked flash such as Samsung's 3D V-NAND or Toshiba's BiCS. There is a consensus that planar NAND will end near the 10nm node, that is, one or two generations into the future from the 15/16nm NAND flash that we at TechInsights are now completing analysis on. We thought it timely to look at some process features that we see in these 15/16nm flash memories.

1Xnm NAND

Table 1: TechInsights receipt of 1Xnm class NAND flash (Source: TechInsights Receipt of 1X nm Class NAND Flash, TechInsights)

We have been buying NAND flash memory for a number of years for our technical analysis reports and Figure 1 shows the process nodes versus year that we acquired them for Micron and SK-Hynix. These two manufacturers were typically the first to market with a process node. A semi-log plot is used to show the roughly 23 per cent/year process shrink (solid black line) that we see for the Micron and Hynix devices.

The rate of process shrinks has slowed dramatically for the 25nm and smaller product and this likely reflects the difficulties in implementing double patterning lithography and reducing electrical interference between adjacent cells.

Observed process nodes

Figure 1: Observed process nodes for Micron and Hynix NAND flash vs. year (Source: Figure 1: Observed Process Nodes for Micron and Hynix NAND Flash vs. Year, TechInsights)

Two approaches can be used for double patterning. Litho-etch-litho-etch (LELE) double patterning (DP) that is typically used for logic processes, or self-aligned double patterning (SADP) using sidewall spacers that is used by the memory makers. This has worked for NAND flash devices down to the present 16nm node but may not make it to the 10nm class of devices.


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