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PCIe IP with system-level data protection targets cloud apps

Posted: 24 Jun 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? cloud? PCI Express? PCIe 4.0?

Synopsys Inc. has expanded its DesignWare IP solution for PCI Express (PCIe) 4.0 to support RAS features to help designers guarantee data integrity and increase data protection in cloud computing SoCs. Additional RAS features boost system reliability by using parity and error correcting code (ECC) data protection together with protocol-defined mechanisms to detect and correct errors in the datapath and RAMs. Event counters and statistics monitor system availability, while error injection and silicon debug capabilities help diagnose issues and validate system recovery, stated the company.

Designers of enterprise systems require increasing levels of bandwidth and that is driving designers to adopt the latest versions of the 16GT/s PCIe 4.0 specification. Even while the PCIe 4.0 specification is under development, Synopsys performs extensive interoperability testing with ecosystem partners to help designers reduce design risk for their initial products with PCIe 4.0.

The DesignWare Controller IP for PCIe 4.0 supports multiple lanes (x1 to x16) and multiple datapath widths for optimal configurations, as well as Native, ARM AMBA AXI-3 and AMBA AXI-4 interfaces for easy integration into SoCs. The DesignWare PHY IP for PCIe 4.0 supports full-featured bifurcation and aggregation, offering designers the flexibility either to configure the PHY macro into multiple individual links at 2.5, 5, 8 or 16GT/s, or to aggregate the PHY macro up to 16 lanes. Synopsys PCI Express 4.0 Verification IP is based on a 100 per cent SystemVerilog, UVM-based architecture with test suites delivered as source code to enable quick development of a verification environment to verify the proper integration and connection of the PCIe interface within the SoC.

The DesignWare Controller and Verification IP for PCI Express 4.0 are available.





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