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Making SoC power grids more robust

Posted: 02 Jul 2015 ?? ?Print Version ?Bookmark and Share

Keywords:SoC? power grid? Power delivery network? PDN? DRC?

SoC design comes with its own set of complixities and challenges. One of the biggest challenges that arise is inherent limitation of particular technology node. As technologies are scaling down, it is becoming more difficult to design the power grid for power hungry SoC with limited power source & inherent limitation of particular technology node. In deep sub?m technology designs, IR drop can often significantly impact the functionality. In this paper, a new methodology is introduced that results in a robust power grid structure. Along with the robust design techniques, this methodology results in better silicon results.

Basics of power grid structure and limitations
Power delivery network (PDN) is the heart of any SoC which supplies power to the entire design. Power grid design of system on chip (SoC) is very important element to build efficient PDN. Power grid should be created such that the worst voltage drop must be meeting across the SoC.

Metals used in the power grid mostly depend on the power requirement of the design & also it depends on metal options used in the technology node. More metal option cost more but it will create more robust design than less metal option design. Metal usage (width, spacing, and metal stack) in the power grid is defined by the power requirement. If we have more power requirement, then in this case we must use metal of more width for the grid. Metal width should be chosen such that no routing track is wasted. Sometimes DRC rules also play a role in deciding the power grid metal width.

Let's have a look on the DRC spacing sample (table 1). DRC spacing rule depends on the metal width & also on the parallel run length of the metal. Below spacing table shows that how spacing varies. If we take M4 power stripe width of w2 um, then in this case spacing from the next M4 signal route of width w1 um (minimum metal width of M4) must be of "s3". M4 width "w2" is chosen to take-care the wide metal rule so that we don't waste the nearby routing track. We are assuming routing grid is of "x" for a particular technology node which may vary from technology to technology. Inherent limitation of technology node forces to leave a gap of 0.01 in both side of M4 power stripe to meet DRC rule. It's called "technology gap". In this way 0.02 um (0.01+0.01) of useful metal resources has been wasted on every M4 stripe of power grid in existing approach. For bigger die size, this technology gap makes significant impact on the grid utilisation & it leads to sub-optimal use of power grid. This technology gap may vary as per power grid metal width selection.

Table 1: Spacing table for a given technology *P1

Figure 1: Illustration of technology gap.

Suggested approach

Figure 2: The proposed approach of power grid design.

Figure 2 shows the proposed approach of Power grid design which is addressed to fill technology gap up-to maximum extent. We have selectively increased M4 metal width from w2 to s4 in such a way that DRC rules are met without using extra routing tracks. Length of "increased width metal" segment is kept at "p1" and space between "increased width metal" segments is "s1"

M4 spacing rule as per DRC rule table:

spacing = s1 if width We have done selective metal width increase throughout the design using utility. We have applied this methodology for metals "M2, M3, M4 & M5" & got significant improvement in capacitance & Reff (effective resistance) of the grid. Table 2 shows the percentage gain in effective resistance seen by instances (Reff) & capacitance of the grid. Increase in grid capacitance will help in dynamic IR drop closure and reduced Reff will address CDM-ESD concerns. Percentage gain (Reff, Capacitance) will go up if design with dense power grid to address high power number is used.

Table 2: The percentage gain in effective resistance seen by instances (Reff) & capacitance of the grid.

Note: Reff gain will change with sheet resistance of metal stack in given technology node.

As seen in the tables, the experiment with selective metal width increase shows a remarkable improvement in power grid capacitance & effective resistance seen by instances in design with respect to traditional power grid design approach. The improvement in grid capacitance for four metal stacks (say M2, M3, M4, M5) is of the order of 10.9% & effective resistance improvement is of the order of 12% with respect to the experiments done without selective metal width increase. The concept of "selective metal width increase" when applied to creating power grid of SOC leads to immense improvement in effective resistance & grid capacitance and also in improved silicon results. For a given dynamic IR drop target, the usage of "selective metal width increase" also leads to saving in the number of power grid lines as compared to normal power grid. By applying suggested methodology we will get the below advantages over the conventional approach:
1. Maximum utilisation of power grid without impacting the routing tracks
2. Improvement in effective resistance of the power grid
3. Increase in power grid capacitance which will help in dynamic IR drop.
4. Significant decrease in resistance of the power grid.

About the authors
Shahab Akhtar, Piyush Mishra, Amit Dey and Azeem Hasan contributed this article.

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