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Examining 3D embedded substrate power packaging

Posted: 03 Jul 2015 ?? ?Print Version ?Bookmark and Share

Keywords:power electronics? through-silicon-via? 3D? Embedded substrate? packaging?

The power electronics industry and the semiconductor industry, inseparably intertwined with one another, are facing unprecedented efficiency, cost, construction and thermal challenges which provide many opportunities for innovation. These industries are in the focal point of the "energy challenge" a multi-faceted problem that involves mobile and cloud infrastructure systems, Internet-of-Things, renewable energy, smart grid, vehicle electrification, and across-the-board power efficiency enhancements in order to keep up with the IT industry's rapid growth in data consumption. These are the competitiveness and sustainability challenges of the twenty-first century.

The paradigm shift we have been experiencing in semiconductor packaging technology was brought about by advanced deep sub-micron semiconductor technology reaching a "cost barrier" that prevented further cost reduction by reducing transistor size and adding more functions to the semiconductor die. This barrier was circumvented through the development of wafer thinning that enabled through-silicon-via (TSV) technology, and the eventual introduction of 2.5D and 3D integration that facilitated heterogeneous ("More than Moore") integration. It will allow the power requirements of the digital load to increase 2 to 5 times, within the same footprint, in a single generation. The power sources community must now find ways to package power sources that will meet this demand, but with no increase in footprint.

In parallel power semiconductor technology is facing a "construction barrier" that prevents realisation of the huge benefits new technology can offer in terms of increased power efficiency and higher power density. These new technologies include gallium-nitride (GaN), silicon-carbide (SiC), and gallium-arsenic (GaAs) power semiconductor devices that require operation in an environment that is free of bond wires and minimises parasitic interconnect elements. The leading packaging technology to achieve a significant reduction in parasitics (L, R, and C) is embedding active and passive components in printed circuit boards (PCBs) and using packaging technologies developed for 2.5D and 3D integration by the semiconductor industry, outsourced semiconductor assembly and test (OSAT) services, and original equipment manufacturers (OEMs). Thus existing 2.5D and 3D integration and component embedding becomes a key enabling technology for high density power sources utilising these new power semiconductor devices.

These multiple factors, led the Power Sources Manufacturing Association (PSMA) Packaging Committee to commission a power packaging study that would focus on 3D Embedded Technology for Power Packaging. PSMA commissioned LTEC Corporation to execute the study from May 2014-February 2015. The 336 page report "Current Developments in 3D Packaging with Focus on Embedded Substrate Technologies" was derived from the research of over 740 published articles, interviews with 30 industry and academic experts, and attendance at 10 trade shows. The purpose was to determine the availability of imbedded substrate technology usable today and in the future by the Power Industry.

The report is intended to assist executives and engineers in their own analysis of how currently available materials and processes could be best used for the creation of advanced high efficiency, high power-density power sources. The report builds upon the findings of the Phase I report ("3D Power Packaging") executed by Tyndall National Institute and issued by the Power Sources Manufacturers Association (PSMA) Packaging Committee in 2014. This article will present the strategic observations and implications based on the findings of both reports.

For the purpose of this article the following definitions apply: Embedded substrate technology is defined as the inclusion of at least one active or passive electrical component within the top and bottom conductive layers of a substrate, with a substrate defined as a planar structure having multiple conductive and insulating layers. A 3D Embedded Power Modules is defined as systems that use a combination of at least one controller/driver IC, at least one active component in the power train, and associated interconnect means, embedded in a single package, where the Z-axis is used to reduce footprint and increase power density.

Embedded substrate technology example
Figure 1 provides an example of this technology based on Shinko Electric Industries Co.'s (Shinko) Moulded Core embedded Package (MCEP) process:

Figure 1: Example of embedded substrate technology (Shinko MCEP).

As part of the project 30 companies were surveyed to determine why they were actively producing or developing power sources utilising embedded technology and at what power level they were considering for this technology. Figure 2a shows the overriding reasons for using the technology was to reduce size (increase power density) and improve performance. Figure 2b illustrates activity at power levels up to and exceeding 1000 Watts.

Figure 2a: Motivations for embedded substrates.

Figure 2b: Power levels under consideration for embedded substrate technology. Totals in Figure 2b add to > 100% as many companies are working at more than one power level.


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