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Implementing JTAG boundary scan

Posted: 08 Jul 2015 ?? ?Print Version ?Bookmark and Share

Keywords:JTAG? IEEE 1149? Boundary scan? ball-grid array? SDRAM?

Several problems may arise when developing a new board. Bare, unpopulated boards can have shorts and opens that can cause circuits not to work or software to fail once the board is populated. After assembly of components, solder bridges of poor solder joints can cause problems. Fortunately, you can employ Boundary Scan, also known as JTAG or IEEE 1149, to find problems that you can then fix.

Boundary scan, based on the IEEE 1149.x set of standards, is the structural testing of printed circuit boards and its installed components. Scan results include information on typical electric circuit faults that occur during PCB manufacturing and include bridging (short circuit) faults, opens, stuck-at faults (stuck at 0, stuck at 1), and line breaks.

JTAG testing is performed on a freshly manufactured board. Figure 1 highlights the process.

Figure 1: The testing stage consists of JTAG Boundary Scan and in-circuit testing.

JTAG testing helps detect opens in BGA (ball-grid array) packages, short circuits, breaks, as well as faulty chips with digital interfaces. It is very important to identify these defects because if an unchecked board gets into a programmer's hands, it creates problems with the launch of memory and other peripherals. It is often not clear what is wrong: programmer's settings, or installation defects. JTAG testing can identify these problems.

The testing stage (before you turn on the circuit for the first time) involves checking the board for short circuits. Then supply voltage is applied to the board and current consumption is checked, after which the main supply voltages are inspected. Then the board is either JTAG or ICT in-circuit tested (you can also run both tests at a time).

Because JTAG comes first, using it to identify problems reduces labour costs in the future. It is logical that if problems are detected after the product's assembly, it will have to be disassembled and reassembled.

The JTAG testing stage reveals:

???Opens in the PCBs with BGA packages, on which ICT testing cannot possibly be done;
???Unsoldered pull-up / pull-down resistors;
???Short circuits.
You can also use JTAG technology to successfully test memory interfaces from SRAM to DDR3 (it only checks the nets integrity, not the memory). This test, combined with the flash memory test, helps send the board to the programmer to install the boot loader and the OS, as well as for subsequent bring-up (first run).

At Promwad, we've used boundary-scan software (figure 2) to perform testing in projects with a miniature set of components, 0402 and BGA packages, high-density layouts, PCBs with more than four layers, and flexible PCBs. Let's explore the use of boundary scan in four specific projects.

Figure 2: Boundary-scan software controls the tests and reports test results.

Case study 1: VoIP Router
Objective: Develop a VoIP telephony device based on the Blackfin BF527 processor with Linux-based software (figure 3).

Figure 3: We performed JTAG and functional testing on this VoIP telephony card, which included SDRAM and flash memory.

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