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Optimise clock synthesis in heterogeneous networks

Posted: 06 Jul 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Small cells? radio access nodes? IP? Power over Ethernet? clock synthesis?

Mobile network operators are increasingly turning to small cell base stations to broaden coverage, boost capacity and enable network densification in congested, high-traffic urban environments. Small cells are low-power radio access nodes that can be used by operators to offload mobile data to Internet Protocol (IP) networks and enable more efficient use of radio spectrum in 4G/LTE applications. Small cells are playing a critical role in helping service providers address escalating bandwidth demand. To fully realise the benefits small cells will provide, small cells must first be optimised in terms of size, power, performance and cost. This optimisation is critical because small cells must be deployed in compact, space-constrained, non-temperature-controlled outdoor locations. Minimal power consumption is important because small cells are often powered using Power over Ethernet (PoE) solutions. To date, significant effort has been made to optimise base band system on a chip (SoC) and digital radio front end performance and integration. This article focuses on a portion of the small cell design that is often overlooked C timing and clock synthesis. New IC architectures are now available that enable lower power, smaller form factor and higher performance small cell clock synthesis.

Architectures for Low Phase Noise Integer-N PLLs
There are two approaches to building chip architectures for low phase noise integer-N PLLs used in small cell applications. Figure 1 shows the conventional analogue architecture used to implement a jitter attenuating phase-locked loop (PLL) for wireless infrastructure applications. This two-stage cascaded PLL architecture uses a discrete, analogue narrowband VCXO-based PLL to implement jitter cleaning in the first loop. The VCXO is used as the PLL VCO because of its low phase noise. The second stage PLL relies on an analogue wideband PLL to provide clock multiplication. The conventional architecture requires discrete loop filter components in addition to the discrete VCXO.

Figure 1: Cascaded PLL Architecture.

Figure 2 shows an alternate approach using Silicon Labs' proprietary fourth-generation DSPLL architecture. DSPLL technology uses a dual-loop PLL architecture with an inner loop and outer loop to realise a low bandwidth jitter attenuating PLL. The inner loop works as a digitally controlled oscillator (DCO) for the outer loop. The inner loop is a wideband PLL based on a low phase noise 15GHz analogue LC-oscillator. Rather than controlling the VCO using analogue circuitry, the oscillator is digitally steered using a high-resolution frac-N feedback divider. The frac-N feedback divider is modulated in precise steps to enable the entire inner loop to operate as a DCO. The LC-oscillator provides a wide tuning range, enabling the inner loop PLL to operate over a wide frequency range. A low-cost fundamental mode, non-pullable crystal is used as the inner loop reference. The loop filter function is implemented digitally without the need for discrete components.

The DSPLL outer loop performs three functions: synchronisation to an externally provided reference clock, jitter attenuation and clock multiplication. Since the inner loop is digitally controlled, the DSPLL outer loop can similarly be implemented using a highly digital architecture. The DSPLL outer loop filter is entirely implemented on-chip using an advanced analogue-to-digital converter (ADC) and digital-signal processing (DSP) based architecture, simplifying printed-circuit board (PCB) layout and design and maximising immunity to board-level noise. An added benefit of this architecture is user-programmability of critical PLL parameters such as the PLL loop bandwidth. The effective frequency tuning resolution of this architecture is 1 part-per-trillion (ppt), enabling very precise PLL control. An added benefit of the DSPLL architecture is no bill of materials (BOM) changes are required to support different input and output frequencies and loop bandwidths.

Figure 2: DSPLL Dual-Loop Architecture.

DSPLL Phase Noise Optimisation
Silicon Labs' proprietary DSPLL architecture has been developed and refined over the last 15 years to provide ultra-low phase noise clock generation for high-speed data converters and 10/40/100G transceivers. This innovative architecture combines both analogue and digital elements to achieve best-in-class integration and performance. Figure 3 illustrates how Silicon Labs' fourth-generation DSPLL has been optimised for phase noise. In this example, all frequencies have been normalized to 1GHz. At close-in offset frequencies, the DSPLL architecture's phase noise closely follows the crystal used as a reference for the inner loop. The DSPLL architecture uses a low-cost, fundamental mode, non-pullable crystal with excellent close-in phase noise. At higher offsets (~1MHz), DSPLL phase noise follows the voltage-controlled oscillator (VCO). Silicon Labs' fourth-generation DSPLL architecture uses an ultra-low phase noise LC-oscillator designed in the most advanced CMOS process node used in the timing industry (55 nm CMOS) to achieve very low phase noise at high offset frequencies. The phase noise at the DSPLL output (shown in dark blue) is a combination of these elements, providing optimal performance in a fully integrated solution.

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