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Is a FinFET + FD-SOI marriage possible?

Posted: 03 Jul 2015 ?? ?Print Version ?Bookmark and Share

Keywords:FinFET? FD-SOI? semiconductor nodes?

Many semiconductor makers choose between FinFET (finned field effect transistors) or FD-SOI (fully depleted silicon-on-insulator). However, more semiconductor manufacturers see the benefit of offering both technologies, especially since foundries like Taiwan Semiconductor Manufacturing Company, Limited (TSMC), GlobalFoundries Inc. and Samsung have to offer both capabilities to their customers.

Freescale Semiconductor Inc., for instance, has just revealed to EE Times that it is using FinFETs for the 14-to-16nm node as well as FD-SOI for 28nm to achieve the same goalfaster speed and lower power consumptionbut for different segments of their semiconductor portfolios. They are also toying with the idea of combining the two for next-generation semiconductor nodes.

SOI Industry Consortium

The SOI Industry Consortium (including IBM, Imec, Soitec and Freescale) has been experimenting with combining FinFETs with SOI, here showing the buried-oxide (BOX, right) which is thinned for FD-SOI. (Source: SOI Industry Consortium)

"Freescale has relationships with all the foundries and has process technologies and connectivity that range from low-complexity to ultra-high-complexity, many of which are proprietary," Ron Martino, vice president of application processors and advanced technology for Freescale's MCU group told EE Times. "As a result, we have developed optimised roadmaps for both FinFET and FD-SOI. FD-SOI wafers are more expensive, for instance, but can be leveraged for low-power or high-performance making them perfect for our 28nm i.MX portfolio. In the case of our digital networking roadmap, we believe the key to success is FinFETs, which achieve their higher-speeds from scaling with a good cost-to-performance ratio."

Martino even suggested that the future may hold some surprises by merging the best-of-both-worlds from the FinFET versus SD-SOI debateperhaps merging the two at next-generation semiconductor nodeswhile simultaneously maintaining the 28nm FD-SOI for lower-end devices for many years into the future.


A diagram of the FinFET on SOI shows how the fins are better isolated and how the undated channel simplifies the processing steps. (Source: SOI Industry Consortium)

"On FD-SOI that requires sensor integration, the 28nm node has the RF and analogue functions needed and for many wearables making it a compelling balance of connectivity and low power," Martino said. "The sweet spot for each node is FD-SOI for 40nm and 28nm and FinFET for the most advanced nodes like 14-to-16nm. In terms of scaling and cost optimisation, we will depend on how effectively we can do that with FD-SOI and FinFET."

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