Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Trends, challenges for EUV lithography

Posted: 08 Jul 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Imec? EUV lithography? extreme ultraviolet? ASML?

Researchers at the Imec research institute have identified small, medium and large challenges on the horizon as they look down the semiconductor road map. During their annual event, they and some of their partners shared a bit of what's in store for the technology.

Reducing costs per transistor at the next-generation, the 10nm node, will be tricky. Even more challenging will be getting extreme ultraviolet lithography (EUV) ready to enable a full 7nm node.

Further out, scaling to and beyond the 5nm node may require a whole new kind of chip technology. Increasingly experts speculate the answer will emerge as some sort of stacking that is not yet on the whiteboard.

The mid-term challenges are currently the most pressing. The 7nm process will be an expensive half node if the long delayed EUV lithography systems are not ready for early production in 2017.

Researchers here are upbeat EUV will arrive in time, but there are plenty of challenges ahead: the light source needs an upgrade to at least 180W, up from today's best demo of 110W at ASML; the systems need to be available at least 80 per cent of the time, up from an average of about 50-60 per cent today; systems need to increase throughput from 70-80 wafers per hour to something closer to the 200w/h of today's immersion steppers; resists need to be more sensitive to work at lower doses with less rough edges; novel protective wafer covers, called pellicles, may need to be designed to replace the initial pellicle ASML is now supplying its customers for use at the relatively low 80W to 110W power levels; and improvements are needed in finding and fixing defects.

Prototype pellicle

ASML is supplying EUV customers a prototype pellicle but may need to redesign it to support stronger light sources on the road map.

"We are confident EUV will enter manufacturing most likely starting at the 7nm node," Luc Van den Hove, CEO of Imec said.

He should know. The institute has spent as much as $1.3 billion on a modern research fab that has been working with EUV systems for years. It houses one of about eight of the latest systems installed worldwide.

Nearly all the top chip makers partner with Imec on pre-competitive research on next-generation nodes. This year Toshiba and Sandisk, two of the few holdouts, joined the programme.

In a talk here, the head of ASML, the Dutch company developing EUV, gave a few new proof points of progress. One customer achieved for one week an 82 per cent up time for one system, the NXE 3300B. ASML has a programme targeting by the end of the year up time of 86 per cent for the volatile light source.

1???2???3???4?Next Page?Last Page

Article Comments - Trends, challenges for EUV lithograp...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top