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Trends, challenges for EUV lithography

Posted: 08 Jul 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Imec? EUV lithography? extreme ultraviolet? ASML?

The system is as critical as it is complex and troubled. Trillions of dollars are at stake in continuing the process of scaling to ever smaller chips, said Peter Wennik, CEO of ASML. "It's a machine with a lot of industrial engineering problems, a whole slew of problems we will resolve one by one," he said.

Indeed every time ASML ratchets up the power on the light source which is critical to the throughput of the machine, some problem emerges in another module that has to be upgraded or redesigned to keep the machine running. "It's a process of continuous engineering," said Kurt Ronse, who heads the lithography programme at Imec.

Without EUV, 7nm is a half node

Today IBM, Imec, Intel, Samsung and TSMC are using at least one of the latest EUV systems. So far most but not all the systems have been upgraded to the 80W light sources. Most of the companies share at least some information on the systems' performance in public forums with the exception of Samsung that has been mum so far.

The next big milestone comes at an EUV conference in October in Maastricht, the Netherlands. IBM, Intel and TSMC have all been invited to speak there.

"We have a lot of non-believers in EUV, but from a technical view it seems we will get there," said Wennik of ASML.

Indeed, observers think the tide may be turning. "We've all been sceptical on EUV, but it seems to be coming together now," said Malcolm Penn, principal of Future Horizons, a market watcher focused on semiconductors.

"There is a strong roadmap on throughput and that gives me confidence EUV will be ready for N7," said An Steegen, who heads Imec's process technology research.

Nevertheless use of the expensive EUV machines will be limited to perhaps three critical layers in a chip. In such layers in a 7nm process, an EUV system can do in a single pass what would take three to five passes with today's immersion steppers.

Immersion litho steps

Without EUV the number of immersion litho steps will mushroom at 7nm.

Steegen believes a direct self-assembly technique, still in the lab, will first be used on the 7nm node. DSA could help reduce the amount of multi-patterning required.

If EUV systems are still not ready for production use in 18 months, chip makers will have to start work on 7nm without them. In that event 7nm will probably become a half node, not a full shrink, said Steegen. Restrictions on chip designers, which already have been significantly narrowed since the introduction of double patterning at 20nm, will get even tighter, she added.

"You relax your pitches and simplify your designs to become more lithography friendly...[and some lines] could require five exposures," she said.

In short, chips would get significantly more expensive to make than ever before. Probably only the largest FPGAs and processors would make use of the process. Profit margins would shrink, belts would get tightened and a lot of people would have a bad day.

In addition to the huge challenges in the lithography for making things, there also is a healthy debate on just what to make at 7nm. Steegen believes today's 3D transistors, FinFETs, will give way to a new style of gate-all-around nanowires.

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