Structural netlist for analogue IP verification

We will be focusing on this problem, and will discuss how to achieve more accurate analogue behaviour by using a structural netlist instead of a behavioural model to reduce the number of silicon defects and the verification cycle time.

SPICE model netlist conversion to structural netlist
This approach talks about using methodologies which directly convert transistor level SPICE model into Structural netlist. The principle of these methodologies is to work by isolating analogue circuits from logic and automatically recognising the latch and flip-flop structures. The design is partitioned into cells, and an automatic algorithm on pattern based function extraction is run. The output is a structural netlist which is used in place of behavioural model for verification purpose. The structural netlist so obtained is pretty much close to actual analogue SPICE model.

Figure 1: Conventional Approach (using behavioural model).

Figure 2: Novel Approach (using Structural Netlist).

Now we will be discussing the advantages of the structural netlist and how this modelling gives us an edge over the conventional behavioural model:

1. The current behavioural models that are used in SOC verification environment don't take into account the voltage modelling. On contrary, in the structural netlist that gets dumped from the SPICE, voltages are also modelled. Thus this approach takes us a step closer towards the actual SPICE behaviour with the use of structural netlist itself. Below is an example of Inverter used in Power Management Controller netlist.

As we can see above, the netlist model for inverter has dependency on the vdd and gnd signals, which will be the case in SPICE and actual silicon as well.

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