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Tearing down Hynix's high bandwidth memory

Posted: 22 Jul 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Hynix? high bandwidth memory? HBM? RAM? through silicon vias?

We have been on the lookout for Hynix's high bandwidth memory (HBM) for the past few months and we finally have one in our lab.

Hynix's high bandwidth memory (HBM) is new and it addresses the bandwidth limitations seen with DDR4 type SDRAM and to some extent DDR5. The technology involves stacking four DRAM dies and a logic die, one on top of the other, with die to die connections being made using through silicon vias (TSVs) and microbumps.

Figure 1 shows the stack of four DRAM dies and logic die affixed to an interposer die. The interposer is used as a routing layer to connect the DRAM to a processor, and to connect the processor to an underlying package substrate.

Figure 1: Schematic cross section of HBM module. (Source: AMD HBM brochure, TechInsights)

Figure 2: Samsung DDR 4 with TSVs (Source: Package Analysis of Samsung DDR4 w TSV, TechInsights)

The quest for improved performance has led AMD to partner with Hynix with their newest series of graphics cards, some of which contain GDDR5 memories and others, Hynix's high bandwidth memory (HBM).

AMD's Fury X GPU with the Hynix HBM is contained inside the metal box labelled Radeon that is seen in figure 3. Two hoses leaving the right side of the GPU carry cooling fluids to a fan unit, while the hoses inside the box terminate on a heat exchanger unit affixed to the backside of the GPU and HBM dies.

Figure 3: AMD Radeon Fury X (Source: TechInsights)

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