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Semicon West highlights 10 chip trends

Posted: 21 Jul 2015 ?? ?Print Version ?Bookmark and Share

Keywords:AMD? Qualcomm? 3D NAND? smartphone? DRAM?

Chip stacks were in the spotlight at Semicon West as a way to compensate for the laws of physics pushing chip makers off the path of Moore's Law. AMD described a packaging victory with its Fiji graphics chip in one session, while a Qualcomm engineering manager warned about manufacturing disconnects ahead in another.

At the transistor level, memory specialists catalogued the challenges and hopes for 3D NAND. In other sessions, lithographers described step-wise progress toward their next-generation systems.

In a sign of the rising importance of chip stacking the International Technology Roadmap for Semiconductors will now focus mainly on packaging-related topics. CMOS scaling, once the focus of the ITRS, has become the territory of a handful of consolidated companies now, said Bill Bottoms, an ITRS participant and CEO of Third Millennium Test Solutions.

"A majority of the improvement in semiconductors going forward will come from heterogeneous integration mainly in complex systems-in-package, bringing things closer together is the only way to get the improvements we need," Bottoms said.

ITRS

ITRS planners see Apple's S1 with 32 components as an example of IoT driving systems-in-package advances.

As an example, he showed a teardown of an Apple Watch with 32 active and passive components packed into it a device Apple calls the S1 SiP. "Smartphones have been the industry driver, but IoT is expected to be the next driver," he said.

The ITRS 2.0 document not yet released will call for ten-fold improvements in the 2.5 and 3D stacks that Bottoms described as "in their infancy" today. For such designs over the next 15 years, costs and power/function need to decrease by four orders of magnitude while the number of point-to-point connections must go up by six orders of magnitude, he said.

Michael Campbell

The cost and complexity of advanced packages are already skyrocketing, said Calvin Cheung, VP of business development and engineering at packaging specialist ASE in Taiwan.

"Our biggest concern is cost," Cheung said. "We used to use a few thousand interconnects in a package, now in a 2.5D device we have a couple hundred thousand interconnects in a very small space," he said.

Qualcomm calls for shared data mining

Creating tomorrow's system-in-package designs will require a new level of data sharing between foundries, packaging houses and chip and system designers. For example, when today's chips are thinned for use in SiP designs they introduce stress factors that packaging companies need to know about, said Michael Campbell, a VP of engineering at Qualcomm.

"There's not a model for yield that takes me from the system and software to the packaging and semiconductor," said Campbell. "Until we got to the 28nm node, you didn't need that level of interactivity between silicon and package and other elements, but now they have to play together," he said.

The problem is "there's no true transfer of wafer or die knowledge to packaging teams to help them accelerate yield," Campbell said. "We need to basically create [packaging] design rules up font and have engineers from packaging houses in our design process up front," he said.

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