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Simplify comm system design, boost available bandwidth

Posted: 30 Jul 2015 ?? ?Print Version ?Bookmark and Share

Keywords:communications systems? analogue-to-digital converters? ADC? amplifier? spurious free dynamic range?

In modern communications systems, the more bandwidth that is available, the more information that can be transmitted. As the requirements for bandwidth increase, the need for faster and higher linearity analogue-to-digital converters (ADCs) and amplifiers also increases. With increased bandwidth, more noise is introduced into the system which can overpower low level signals of interest. This places added requirements on the ADC and amplifier to have low noise. Also with increased bandwidth, the linearity of the system becomes more critical, especially in the presence of a strong interferer which can block other signals of interest. One approach to resolve these issues is to use a high speed, high resolution ADC with an equally fast amplifier driving it. This will allow better sensitivity and selectivity of the receiver, and will ultimately improve the quality of the system.

Basic introduction to communications system design
There are several fundamental design trade-offs in any communications system. Bandwidth, spurious free dynamic range (SFDR) and sensitivity are all important factors in a communications system, but are difficult to achieve with a single solution. The usable bandwidth of a system is heavily dependent on the sample rate of the ADC. The bandwidth of the system cannot be greater than half the sample rate of the ADC. For more bandwidth, faster sampling is required, which limits the range of practical ADC options. High speed ADCs are typically lacking in terms of SFDR and signal to noise ratio (SNR), limiting the performance of the receiver.

However, the LTC2107 210Msps 16bit ADC sets a new level of performance with excellent linearity. With a sample rate of 210Msps, the usable data bandwidth is nearly 105MHz, and with an SNR of 79dB, very low level signals can be detected. The LTC2107, coupled with a high linearity amplifier like the LTC6409, improves the throughput of modern communications systems while simplifying the front-end design.

Trade-offs and challenges
A major challenge in high speed communications design is maintaining good SNR while maintaining wide bandwidth. Designers face trade-offs among the various approaches. One approach is to use slower sample rates and higher order filters to attenuate the out-of-band noise before the analogue input signal is sampled. This requires a complex filter network with several stages of attenuation, requiring a significant number of components. High order filters also tend to ring in response to the sampling glitches of the high speed ADC. This problem is solved by using an ADC with a faster sample rate. This simplifies the analogue filter design.

Using a low order filter allows the sampling glitches to settle properly and improves the linearity of the system. Using a high speed ADC, such as the LTC2107, solves the design problem in a simplified and elegant way. With a sample rate of 210Msps, there is more than enough bandwidth for any demanding communications system. With a wider bandwidth, the anti-aliasing filter used to reject out-of-band signals becomes easier to design. With more bandwidth as a guardband, the filter used can be lower order, making it easier to design and reducing component count.

A wider bandwidth allows more noise to be sampled by the ADC, increasing the need for an ADC with a high SNR. The SNR of the LTC2107 is 79dB. The device's improved SNR and SFDR allow the receiver to accept lower level signals that could be buried in the noise floor of noisier parts. This adds range to the receiver and allows signal transmission over longer distances. The high SNR and SFDR of the LTC2107 improve system performance without sacrificing bandwidth.

Best design practices: Symmetry, absorptive network

High performance ADCs require a high performance environment in which to operate. With any direct sampling ADC, non-linear charge is produced in the sampling process. This charge is reflected into the input network each time the sampling switches close. A highly absorptive network is required at the analogue input to ensure that none of this charge is reflected back into the input network where it can potentially be re-sampled. The input network of the ADC should be as close to 50? as possible to allow for maximum absorption of this non-linear charge. If this charge is reflected in a less than ideal reflective network, it can be re-sampled by the ADC and result in simple distortion or intermodulation distortion.

Another potential source of distortion is an asymmetrical layout of the input network. Nearly all high speed ADCs are differential by design. With an ideal layout, this allows excellent common mode rejection and very good 2nd order harmonic distortion. Any deviation from perfect symmetry will cause a mismatch in the differential signals which will manifest itself as 2nd order harmonic distortion. Even a simple design decision to flood copper closer on one side of the differential pair than the other side can cause a difference in ground current in the adjacent ground planes. This adds distortion to the system. Absolute symmetry is required for maximum performance. Figure 1 shows an example of good layout of a high speed ADC. This symmetry should extend several centimeters beyond the ADC or to the nearest amplifier or balun transformer.

Figure 1: Proper layout for the LTC2107.

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