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Semicon West highlights path towards 3D IC

Posted: 27 Jul 2015 ?? ?Print Version ?Bookmark and Share

Keywords:3D IC? Semicon West? Imec? Globalfoundries? TSV?

There was a resounding theme during the recent Semicon West: the roadmap forward is 3D IC. Yes, we can and we will keep pushing dimensions down, which for a few applications would be attractive, but for most designs the path forward would be "More than Moore."

As Globalfoundries' CEO Jha recently voiced: "It's clear that More-than-Moore is now mainstream rather than niche...Really it is leading-edge pure digital that is the niche. Instead the high-cost leading edge processes are really niche processes optimised for applications in data centres or for high computational loads, albeit niches with volumes of hundred of millions of units per year." Similarly, EE Times editor Rick Merritt subtitled his Semicon West summary, Roadmap being drawn for chip stacks. All this is nicely illustrated by the following slide presented by An Steegen of Imec for their pre-Semicon Technology Forum:

Pre-Semicon Technology Forum

A slide presented by An Steegen of Imec for their pre-Semicon Technology Forum

Leti, the other major semiconductor R&D organisation, has gone even further by dedicating its Semicon West day entirely to 3D technologies, as can be seen in the following invitation:

3D technology

A similar view was also presented by Intel. Quoting Jeff Groff from his summary of Intel's Q2 call: "In summary, it seems that Intel is executing fairly well on the process technology side of the business considering the ever increasing difficulty of pushing forward with Moore's Law. We can expect exciting new structures and materials (just maybe not at 10nm) and an increasing importance of 3D structures in both logic and memory fabrication." This echoes our blog Intel Calls for 3D IC, and was recently voiced by Intel's process guru Mark Bohr: "Bohr predicted that Moore's Law will not come to an abrupt halt, but will morph and evolve and go in a different direction, such as scaling density by the 3D stacking of components rather than continuing to reduce transistor size." It is also illustrated by his slide from ISSCC earlier this year.

Moore's Law

The two concerns regarding 3D IC stacking using TSV are (a) Cost, noted in the slide above "Poor for Low Cost," and (b) Vertical connectivity, as voiced by Mark Bohr: "Intel's Bohr agrees that 3D structures will become more important. He said the kind of through-silicon vias used for today's chip stacks need to improve in their density by orders of magnitude."

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