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A closer look inside SK Hynix's 1st high bandwidth memory

Posted: 28 Jul 2015 ?? ?Print Version ?Bookmark and Share

Keywords:high bandwidth memory? HBM? GPU? graphics card? DRAM?

Korean memory chipmaker SK Hynix finally showed its high bandwidth memory (HBM) module in a downstream product after announcing it early last year, claiming it to be the world's first 8Gbit module developed using 2Gbit, 20nm node, DDR4 SDRAM. The HBM module appears in AMD's Radeon 390X Fury X graphics card.

We at TechInsights have a few of the Fury X cards in our lab and its GPU unit is shown below in Figure 1. The GPU die is seen in the centre of the module with four Hynix HBM memory modules arranged around its perimeter. Both the GPU and the HBM modules are flip-chip bumped to a UMC fabbed interposer. This interposer is, in turn, bumped to a laminate substrate. The GPU is massive measuring in at 23mm by 27mm large, and is believed to be fabricated using TSMC's 28nm HKMG process.

The HBM uses through silicon vias (TSVs) to connect the DRAM dies and base logic die together, and this is a fairly new technology for DRAM. Samsung has a 20nm DDR4 with four stacked DRAM dies with TSVs, but this part is not a wide I/O device, nor does it contain a base logic die. Hynix's HBM has a 1,024-wide bus qualifying it as wide I/O. It employs a base logic die as an interface between the four DRAM die stack and an interposer that supports both the HBM modules and the AMD GPU. The HBM can be considered 3D packaging, while the laterally spaced apart layout for the GPU and HBM modules on the interposer makes for a 2.5D package.


Figure 1: AMD Fiji GPU with Hynix HBM memories (Source: Detailed Structural Analysis of the SK-Hynix HBM, TechInsights)

Figure 2 is a SEM cross section of the Hynix HBM module showing the four DRAM dies, the base logic die, the AMD interposer and the laminate substrate. The bottom three DRAM dies have been thinned, while the top DRAM die is considerably thicker. The thicker top DRAM die is likely a deliberate design feature, and is possibly being used to add mechanical stiffness to the HBM module. Microbump structures connecting the dies together and to the interposer are just visible in this image.

HBM memory

Figure 2: Hynix HBM memory (Source: Package Analysis of the SK-Hynix HBM, TechInsights)

The TSVs used to connect the stacked DRAM dies together can be seen in Figures 3 and 4. A via middle process is used to form the TSVs, where the wafers have undergone their front end of line processing (FEOL) to make the transistors, their contacts and pre-metal dielectrics. A reactive ion etch was likely used to make the TSV openings. The vias have a slight taper, with the top portions of the vias, nearest the active circuitry, being slightly wider than the bottom portions.

Stacked DRAM dies

Figure 3: Stacked DRAM dies and TSVs (Source: Package Analysis of the SK-Hynix HBM, TechInsights)

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