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IBM, Macronix give PCM drift one more shot

Posted: 04 Aug 2015 ?? ?Print Version ?Bookmark and Share

Keywords:IBM? Macronix? PCM drift? SCM memory?

IBM and Macronix have demonstrated an innovative approach to the problem of a 2bit/cell MLC drift. The different approach was to find a means of reducing the statistical spread of the resistance levels of the MLC. This would mean in the presence of drift, the distributions would take much more time before the resistance values for different MLC data levels overlapped, resulting in a read failure.

There are two possible ways to obtain the middle two levels of the four levels of a 2bit/cell MLC. One is to SET a cell to its low resistance state and then progressively RESET it, using read verify to stop when the required resistance level is reached. Or, alternatively, RESET the cell then progressively SET the cell with a series of SET pulses again until the desired resistance level is reached. The IBM team elected to use an iterative SET/verify scheme to achieve the four resistance levels required for a 2bit/cell MLC.

The reason for this choice is the IBM authors discovered that for a 2bit/cell PCM the spread of the "10" logic state resistance was relatively small as a function of current, but the spread of the "01" data state resistance of a 2bit/cell always had a wider spread, irrespective of the means used to achieve it. They accounted for this by the observation that the broad spread occurs whenever the current levels are such that melting occurs during either SET or RESET; during RESET it always occurs. However, the SET step is not usually associated with melting as the crystallization temperatures are much lower than the melting temperature.

In the past there has been much debate about when and how much melting occurs during SET and the volume of material involved. The reasons why melting is required during SET was well exposed by the recent definitive work from IBM (Zurich) on crystal growth rates. That work established maximum crystal growth rate, the shortest SET time, occurred near the melting temperature. The figure below shows from temperature profile and the volume of molten material during SET at different current levels for in this case a 55nm size "dome" device. The small red arrows mark the molten interface as higher crystal growth rates are required.

PCM drift

(a) Examples of temperature profiles and melting for different SET currents, (b) the possible profile for the I(melt) current


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