3D stackable non-volatile RRAM enables 20GB arrays

A group of researchers led by James Tour, professor at Rice University, has developed a 3D stackable non-volatile resistive random access memory (RRAM) that claims to surpass competitive designs in both speed and bits-per-crossbar. They were able to do this by combining a novel architecture, room temperature processing and a high-density resistive material stack.

The key is a material stack that has a built in Schottky contact per bit thus taking the place of the diode required by the most efficient designs to date, and he claims it sports ultra-low leakage (sneak) currents, thus enabling up to 162Gb (20GB) crossbar arrays.

"Our group's ultrahigh-density non-volatile resistive memory uses a 3D material that can be fabricated at room temperature," Tour said. "Each device shows excellent selector-less memory on-off ratios, higher than 10 at 3.6V."

The Tour group at Rice has been working on RRAMs for many years, and has licensed previous versions for manufacturing. Its previous RRAM design using silicon dioxide as the active material has been licensed by a Tel Aviv-based company called Weebit Nano Ltd, according to Tour.

Layered structure of tantalum oxide, multilayer graphene and platinum used for a new type of resistive random access memory (RRAM) memory, rectangular box depicts bit cell detailed below. (Photo: James Tour Group) (Source: Rice University)

"Weebit in Israel has licensed our previous work on resistive memories which uses many of the same principles as our newest design," Tour stated.

The current materials stack has many refinements over the original design. What's common is that the two-terminal resistive material is sandwiched between metallic crossbars, the density of which determines the density of the memory array. The density of the array, in turn, is limited by the ratio between the "on" resistance compared to the "off" resistance, 10-to-1, for the current material, compared to the leakage (sneak) current through adjacent memory cells that are not being addressed (crosstalk).

Tour's current material stack has very little "sneak" crosstalk when addressing the two-terminal bit cells in-between the x- and y-crossbar lines, enabling up to 162Gb (20GB) memories to co-exist in a single crossbar.

Electron microscope image of bit-cell (rectangular area in figure above) showing layered structure of tantalum oxide, multilayer graphene and platinum that overcomes crosstalk problems causing read errors in other designs. (Photo: James Tour Group) (Source: Rice University)

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