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Agile techniques for hardware design (Part 2)

Posted: 26 Aug 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Software? Waterfall? hardware? FPGA? Agile?

We asked readers of Part 1 to guess the cost of a prototype run of 28 nm chips, as Agile development relies on a sequence of interim prototypes versus the One Big Tapeout of the traditional Waterfall process. Here are the results:

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The surprisingly low manufacturing cost of prototype chipsone fifth the readers' estimatemeans Agile development is eminently affordable, even for academics. It also calls into question the current high cost of designing SoCs using the Waterfall process. Having established Agile's viability, based on our experience we propose four guidelines to lower development costs.

1. Be scalable to minimize die size
Manufacturing costs for prototype dies are linear in area; a 10 x 10 mm die is 40 times the area of the smallest die, so it costs 40 times as much, or $1.2 million. Thus, you want a scalable design that you can manufacture in its smallest configuration.

At 28 nm, even the smallest die has a lot of transistors. This tiny chip can fit a couple of million logic gates with some memory and I/O. For example, the smallest die has room for two 64-bit, dual-issue, out-of-order execution RISC-V cores with dual 32 KB caches, with a quarter of the die left for other IP. The manufacturing costs in the most recently available technology for multichip projects (28 nm) are higher per unit area, but nearly twice as many gates fit. As a result, the manufacturing costs per functional unit are actually less in the newest technology!

2. Follow Agile to reduce cost of verification and validation
Much of the $30M to $100M SoC cost are hardware design and verification, with more spent on verification than on design.

One reason is the use of Waterfall development, with the assumption of a One Big Tapeout near the end of the process, which causes engineers to run simulations for CPU-centuries in the hope of having a working chip on first silicon. Clearly, the Agile approach of a sequence of prototypes needs less simulation effort since hardware prototypes run orders of magnitude faster than simulators. To ameliorate the long latency of a chip fab, we do some Agile iterations using FPGAs, as our design system (Chisel) can produce both the EDIF for FPGAs and chip layout from a single design. FPGA prototypes run 10 to 20 times slower than chip prototypes, but that is still much faster than simulators. While there are some benefits in verification ("build the thing right"), where Agile really shines is validation ("build the right thing"), in that you're more likely to meet energy-performance expectations using the iterative Agile process.

3. Follow modern programming techniques to enhance reuse
The major reason for the high cost of design and validation/verification, however, is the lack of reuse. Except for licensed blackbox IP (for CPUs, GPUs, buses, and I/O devices), nearly everything else is designed from scratch. Even when such ad hoc reuse is tried, it must be verified as if it were custom, as minor mismatches between its original use and the intended application are a common source of bugs.

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