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Agile techniques for hardware design (Part 3)

Posted: 28 Aug 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Software? Waterfall? hardware? FPGA? Agile?

In Part 1 we defined Agile hardware development as a process of designing a sequence of working but incomplete prototype chips by a small team, rather than One Big Tapeout at the end of a Waterfall process.

In Part 2 we showed that a 28 nm prototype run can cost only $30,000, which calls into question the high cost of designing SoCs using a Waterfall process. We offered guidelines to lower costs:

1. Have a scalable design so that you can use the lowest-cost die for the prototype run.
2. Reduce the cost of verification and validation by iterating Agile prototypes.
3. Reduce the cost of design and verification by leveraging ideas from modern programming languages that increase reuse.
4. Reduce software SoC costs by having IP enhance a common, small, free instruction set like RISC-V to reduce the number of software stacks

This article is inspired by guideline 3) above. Berkeley RISC-V chips use Chisel, a domain-specific hardware description language embedded in Scala. Scala is one of the recent languages that includes many modern techniques to enhance reuse. The result of "executing" the Scala program is the generation of Verilog code.

Chisel generators capture the architectural decisions, and particular processor instances are produced from a single microarchitecture. Indeed, our three RISC-V designs share most of their code, even though the designs were not done at the same time nor by the same people.

One particularly powerful example of a programming language technique in Chisel that enhances reuse is functional programming. It is a declarative style of programming with no state, so you write expressions that are side-effect free. Thus, the output depends solely on the inputs, which makes the execution of functional programs easier to understand and, ultimately, test.

We describe a crossbar switch as an example, which was presented by Yunsup Lee at the second RISC-V workshop. It connects two AHB-lite busses as masters (io.masters) to three AHB-lite slave multiplexors (io.slaves).

The figure below shows our high-level goal on the left, the two building blocks in the middle, and the final design on the right.

Before building a crossbar in Chisel, let us review a few generic functional idioms. The first maps a list of numbers to an expression that increments them. Thus

(1, 2, 3) map { n => n + 1 }

produces the output

(2, 3, 4)

The zip operator "zippers" or joins two lists together. Thus

(1, 2, 3) zip (a, b, c)

produces the output

((1, a), (2, b), (3, c))

We can map over tuples and use Scala's case statement to provide names for them, and then operate on those names accordingly

((1, a), (2, b), (3, c)) map { case (left, right) => left }

produces the output

(1, 2, 3)

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