Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Mystery in memory: Why 3D XPoint is not PCM

Posted: 01 Sep 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Intel? 3D XPoint? PCM? memory? NVM Express?

From that curve it was possible to estimate for a planar PCM memory cell structure the SET time for devices with an inter-electrode spacing of 50nm and 10nm as illustrated. Clearly a PCM device with a 10nm inter-electrode gap has a sub 20ns SET time and reducing it to 5nm would provide a SET time in the 1ns to 10ns range.

The problem is every time the inter-electrode space is reduced, a penalty must be paid in data retention time at elevated temperature, or the non-volatility performance, as shown in the right hand side of the second image. The potential problems mount to get the minimum device SET time, and the maximum crystal growth rate requires maintaining the crystallizing interface at a temperature close to the melting temperature. This means there will almost certainly be molten material within the cell during the SET operation. With close packed stacked devices, the effects of heating and thermal cross-talk becomes a problem during both SET and RESET.

Crystallisation

So all that is required for 3DXPoint to be chalcogenide PCM-based is for Intel/Micron to have found or developed a new phase change memory material that at a low temperature has a high crystallisation rate, equal or better than that of GST close to its melting point, combined with an activation energy of crystallisation that moves its crystallisation rate at elevated temperature well outside the planned operating chip temperature range.

If the general form of the curve in the second image is the same for most phase change compositions then this new material as described above would not allow much variation in SET current before the write time was compromised.

A new active material, which when crystallised for the memory SET state, would need to have to a high electrical resistance combined with a low melting temperature. A lower melting temperature would reduce any thermal cross talk effects, while the lower RESET current resulting from the higher resistance would act to reduce the damaging effect of element separation on write/erase endurance and data retention caused by electro-migration.

The above deals only with the memory device and there is a separate problem in finding a matrix isolation or selection device that is closely coupled to the memory in the 3DXPoint 128Gb array.

Is it possible that Intel/Micron have found or developed such a Golden++ material from the chalcogenide family of compounds? Or is there some property of the chalcogenides that has not yet been exploited? On the balance of probability my answer would be no. I would look somewhere else for what is under the hood of 3D XPoint.

- Ron Neale
??EE Times


?First Page?Previous Page 1???2



Article Comments - Mystery in memory: Why 3D XPoint is ...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top