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Spot IGBT degradation through power cycling

Posted: 17 Sep 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Dissipated heat? IGBT? 3D? power cycler? thermal interface material?

Because of the short heating time, the maximum temperature elevation of the substrate-base plate joint was 71C, but the die-attach temperature increased by more than 100C. This result indicated that the most vulnerable point of the structure was the die-attach material.

The periodically measured thermal transients allowed us to generate structure functions corresponding to various number of applied power cycles. Figure 11 shows the effect of the generated power cycles on the structure functions corresponding to every 5,000th cycle. After the first capacitive step, the flat region corresponded to the die-attach material. The structure was stable until 17,000 cycles; however, after that point, the degradation of the die-attach material was obvious, and its resistance increased continuously until the device failed.

Figure 11: Structure functions of sample 0 corresponding to control measurements at various time points show different failure points.

As shown in figure 12, we divided the thermal resistance of the die-attach layer that was read by the initial junction-to-ambient resistance of the system and plotted it as a function of power cycles. This calculation confirms that the degradation of this layer started soon after 15,000 cycles. The heat-flow path changed so dramatically because of the significant change in the die-attach material that it was impossible to investigate the latter structural elements. However, degradation in the latter sections could be reasonably expected as well, but they would be negligible compared to the problem with the die-attach material.

Figure 12: Thermal resistance of the die-attach layer relative to the junction to ambient thermal resistance in the initial state show the point of failure.

After approximately 20,000 cycles, the effect of the die- attach degradation was significant, and in about 10,000 cycles, the total junction-to-ambient thermal resistance of the sample doubled as a result of the cycling. After 30,000 cycles, we were unable to determine the exact thermal resistance of the die-attach layer because of the changes in the heat spreading path.

This work was partially supported by the 288801 SMARTPOWER integrated project of the Framework 7 Program of the EU. This information was originally presented at the Electronics Packaging Technology Conference.

About the author
Andras Vass-Varnai obtained his MSc degree in electrical engineering in 2007 at the Budapest University of Technology and Economics. He started his professional career at the MicReD group of Mentor Graphics as an application engineer. Andras managed technically the EU-funded Nanopack FP7 project on behalf of Mentor Graphics, resulting in the development of DynTIM, the Mentor Graphics thermal interface material (TIM) measurement solution. Currently, he works as a product manager responsible for the Mentor Graphics thermal transient testing hardware solutions, including the T3Ster product. His main topics of interest include thermal management of electric systems, advanced applications of thermal transient testing, characterisation of TIM materials, and reliability testing of high power semiconductor devices

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