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Examining the most underrated FPGA design tool ever

Posted: 22 Sep 2015 ?? ?Print Version ?Bookmark and Share

Keywords:FPGAs? high level design? OpenCL? MATLAB? VHDL?

There are other model-based tools on the market, such as HDL Coder, Synplify, and System Generator; however, only DSP Builder Advanced Blockset offers the combination of the following ten features:

???Decoupling of system data rates from FPGA clock rates; native multi-channel capabilities.
???Automated timing closure at high Fmax, including auto-pipelining.
???Deterministic latency and data throughput.
???Optimal usage of FPGA hard block features.
???Design portability across FPGA families.
???Fixed- or floating-point numerical implementation.
???Support for vector manipulation.
???Math.h library.
???System simulation in the Mathworks' environment.
???Hardware simulation from the Mathworks' environment.
This combination is what allows the tool to deliver superior QoR along with the productivity advantages of a high level simulation, design, and verification tool flow. Let's look at each of these features in a little more detail...

Decoupling of system data rates from FPGA clock rates
Using DSP Builder, the user specifies the desired design clock rate. The data rate can be higher or lower than the clock rate, sometimes dramatically so. The tool will automatically parallelise the data and represent the data buses as vectors in cases where the data rate is higher than the clock rate. Integer ratios work most efficiently (4, 8, 12, 16, 32...) but any ratio will work and the control path will insert empty data into some of the vectors to accommodate this.

This capability provides the ability to support very high data rates of many GSPS using realistic FPGA clock rates of several hundred MHz, depending upon the FPGA family.

Figure 2: From FFT, to parameter file, to parameterizable design.

Within DSP Builder, the designer builds the datapath, often containing various rate FIR filters, memory blocks, NCOs, mixers, saturate and round blocks, and so forth. However, the designer need only lay down a single channel datapath assuming the design clocks at the required rate, regardless of the actual data rate. DSP Builder will build the data path with the specified number of channels, and vectorise (or parallelize) the design to achieve the needed data throughput. This is specified in a parameter file, which means it is easily changed, with the only effort being a recompile. The tool generates all needed control logic to handle multi-channel and higher data rates, even for complex datapaths. Further all configuration or coefficient registers can be read or written, with the addressing and accessing logic auto-generated. This will operate at a lower clock rate than the datapath.

Automated timing closure at high Fmax, including auto-pipelining
Most high-level design tools output Verilog or VHLD files, which the FPGA vendor's synthesis, fitter, and routing tools then use to try to achieve the best possible clock rates coupled with the most compact logic implementation. The generated code is generic, relying on the FPGA vendor tools to map into a particular FPGA architecture and speed grade.

In contrast, the DSP Builder tool works with the user-specified clock rate, FPGA family, and FPGA speed grade to auto-generate optimised Verilog or VHDL (your choice) code. One key aspect of this is auto-pipelining. The designers will have register stages throughout their design, but only the registers that are algorithmically necessary. For example, a FIR filter has a specific number of data register delays between taps, or an IIR filter has a specific feedback path register delay. DSP Builder will read the specific timing parameters for the chosen FPGA/speed grade, andbased on the desired clock ratewill add the appropriate stages of pipelining registers. This customises the auto-generated code for that specific FPGA, balancing latency, and register resources so as to achieve the required clock rate.

Figure 3: User design is algorithmic. The tool handles the optimised implementationencapsulating and automating Altera's internal knowledge on how best to optimise for our FPGA devices.


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