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Examining the most underrated FPGA design tool ever

Posted: 22 Sep 2015 ?? ?Print Version ?Bookmark and Share

Keywords:FPGAs? high level design? OpenCL? MATLAB? VHDL?

Due to the high Fmax and low logic usage of the math library, designers no longer need to craft their implementations to minimise use of functions such as divide, square root, trigonometric, logarithm, and exponent operators.

System simulation in Mathworks' environment
Complex algorithms must be developed and verified at the system level. Model-based designs allow the system engineer to leverage the extensive capabilities and toolboxes of Mathworks products. Oftentimes, the test bench can be more complex than the algorithm being implemented, so the ability to simulate using MATLAB and Simulink is extremely useful.

Figure 12: Bit- and cycle-accurate Simulink simulation, automatic verification in RTL simulation, and 'System In The Loop' verification on connected hardware.

The DSP Builder design can also be simulated within the Mathworks environment, thereby allowing full visibility and easy debug before any hardware is involved. DSP Builder will also provide resource estimations (e.g., logic, DSP blocks, memory) without the need to perform any FPGA compiles, which can be fairly time-consuming. This allows for rapid design space exploration, enabling the designer to make trade-offs and ensure the design will fit into the chosen FPGA prior to invoking synthesis, fitting, and routing. Furthermore, DSP Builder will generate a ModelSim testbench using the same vectors generated by Mathworks testbench, and also run the hardware verification. This certifies the fidelity of the DSP Builder code-generation process, ensuring the behaviour observed in the original Mathworks simulation is faithfully reproduced in hardware.

Hardware simulation from the Mathworks' environment
A further option is provided to accelerate verification. Rather than running the simulation on the x86 CPU, there is an option to run on the actual FPGA hardware. This capability is naturally called "FPGA in the Loop" or FIL. In most cases, FPGA development boards are readily available andusing a USB connection between the development machine and FPGA hardwarethe actual processing can be performed in real time on the FPGA. The input and output data is buffered, and the FPGA is throttled to operate at the rate data can be supplied and retrieved. For high GFLOPS or GOPS algorithms, this can provide dramatic speedups in system verification, along with the added piece of mind that the actual implementation hardware is being exercised.

In conclusion, the best way to convince sceptical engineers who will actually have to rely on the tool is to provide representative, complete, open source design examples. These are currently available, and many ship with the tool itself.

Figure 13: Screenshot of some of the demonstration designs shipped with the tool.

The performance, resource utilisation, and design methodology of a few of these example designs will be detailed in future articles as follows:

???High throughput FFT, 4K points at 10 GSPS.
???4 GSPS Digital Up-conversion.
???Wideband Beamformer with picosecond resolution.
???4G Remote Radio Head including CFR and DPD.
???Cholesky and QRD matrix solvers in single-precision floating-point.
???SAR radar in single-precision floating-point.
???Short-range FMCW radar in low-cost FPGAs.
???Field-Oriented Motor Control in floating-point in low cost FPGAs.
???Space-Time Adaptive radar in single-precision floating-point.
This combination of designs serve to showcase unique capabilities that are not only unavailable in competing high-level design tools, but are often extremely difficult to implement in traditional Verilog or VHDL designs. In fact, many customers have adopted DSP Builder Advanced Blockset precisely because they ran into difficulties using traditional toolflows, and were only able to achieve their design goals using the DSP Builder design flow.

About the authors
Michael Parker is Principal DSP Product Planning Manager at Altera.

Mark Jervis is DSP Engineering Tools Manager at Altera.


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