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Enable 10Gbit/s physical layer for single twisted pair

Posted: 23 Sep 2015 ?? ?Print Version ?Bookmark and Share

Keywords:advanced driver assistance systems? ADAS? single twisted pair? STP? complementary metal oxide semiconductor?

Applications such as advanced driver assistance systems (ADAS) and passenger infotainment drive data rates in automotive vehicles. To realise the lightweight and fuel efficient cars of the future, it is mandatory to increase the data rate, to get more bits over the same channel in the same time. This article introduces an elegant method to increase the data bandwidth in a single twisted pair (STP) cabling.

High data rates in vehicle networks could be achieved through multiple technical approaches. On the one hand this goal could be achieved by investing effort in the channel/transmission medium (see [1]). However, there is always the conflict between electrical requirements, like transfer function and electro-magnetic radiance/ susceptibility, and mechanical requirements, like weight, diameter, stiffness and used materials. The mechanical requirements indirectly stand for usability and costs of the cables. On the other hand, the goal of a higher data rate through the same channel can be achieved by investing in the signal processing at the end points. The development effort takes place up front and the only material costs are increased silicon area. Operating costs will rise by only the (unavoidable) power consumption in the network node; however, the goal of a new physical layer will be not to raise the power consumption per transmitted bit/s. The second option is the main focus of the presented work and technology.

The challenge
Major use cases for high-speed data transmission in vehicles are low-latency uncompressed video transmission and a network backbone of consolidated connections and busses. For the next generation of networks, data rates in the range of 10Gbit/seven up to the 12.5Gbit/s required for high-resolution video distribution C are targeted. As a reference, application-proven lightweight cables like the star-quad are taken as a possible candidate for the transmission medium. Achievable lengths should be 10-15 m. At the targeted speeds, the transfer function of common cables becomes more problematic. Higher attenuation at higher frequencies surpasses practically compensable insertion loss in almost every cable type. Moreover, in certain cable types there is a notch present in the signal band in the frequency range from 2GHz to 3,5GHz. [2]

Furthermore, standard complementary metal oxide semiconductor (CMOS) technology itself becomes more bandwidth limiting at the target speeds. The parasitic transistor capacitances and a limited maximum transit frequency, and the ESD (electro-static discharge) protection at the pads, have a major influence on the transfer function of the channel. Additionally, the targeted speed conflicts with transmit power requirements for the cable lengths common e.g. in automotive applications. It is therefore the specific goal to increase throughput by adding intelligence on the semiconductor side and keeping the transmission medium light and low-cost. The core requirements selected for the development of the new physical layer were chosen to be a low deterministic latency, low power consumption, and the use of a single twisted pair. The target bit error rate was fixed at 10-12. The implementation had to be feasible on a standard CMOS process.

System overview
To tackle the design problem at hand, it was necessary to undertake a paradigm shift and abandon classical NRZ (non-return-to-zero) binary coding with relatively slim signal processing. Firstly, we moved to a higher level modulation format and thereby limited the transmission bandwidth, which is now well below the notch of conventional twisted pair cables. The choice for the modulation format was also made through the calculation of the so-called channel capacity of the chosen cable. (The channel capacity gives a theoretical maximum of achievable data rates; practical implementations are well below that number.) This calculation showed that binary coding at available transmit powers could not carry a 10 GBps data rate. It also showed which modulation complexity would yield optimal data rate performance on the channel. Secondly, the signal processing was moved into the digital domain to acquire more complex and powerful signal processing algorithms.

More specifically, a PAM4 modulation format was chosen. To facilitate the signal processing in the digital domain, a high-speed Digital-Analogue-Converter (DAC) and an Analogue-Digital-Converter (ADC) were implemented. The cable transfer function (low pass characteristic) is now compensated by two digital filters at transmitter and receiver working in tandem. These filters are adapted at run-time. The bit error rate is achieved and secured by adding error correcting redundancy encoding and decoding to the transmission system (so-called forward error correction).

CMOS implementation
Fraunhofer IIS has developed a hybrid prototype of an ASIC (application specific integrated circuit) and an FPGA (field-programmable gate array) to implement all these features of the new physical layer. The analogue frontends (DAC and ADC) were implemented in the ASIC. This allows evaluation of the real circuit performance with all parasitic effects and getting reliable estimates for the overall power consumption, once analogue and digital functionality is integrated together on a single chip. Moreover, with this implementation, the highest risk in system development was already addressed and the feasibility of the complete system could be shown.

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