Synopsys rolls out IP line for TSMC 10nm FinFET process

Synopsys Inc. has successfully tape-outed a line-up of DesignWare Interface and Foundation IP on TSMC's 10nm FinFET process, minimising the risk for designers who want to take advantage of the power, area and performance improvements offered by the process.

Achieving this tape-out milestone allows designers to speed the development of SoCs that incorporate USB 3.1, USB 3.0, USB 2.0, HSIC, PCI Express 3.0, PCI Express 2.0 and MIPI D-PHY interface IP, stated the company.

In addition, Synopsys is developing embedded memories, DDR4, LPDDR4 and MIPI M-PHY IP, which will further extend its 10nm IP portfolio. TSMC's 10nm process provides 2.2 times the logic density, a 15 per cent performance improvement, and 35 per cent power reduction compared to their 16nm FinFET Plus process node. Taking advantage of the process, Synopsys has re-architected its IP at 10nm for lower power, higher performance and smaller area compared to the previous generation. As an example, the high-speed SerDes-based PHYs consume less than 5mW/Gb/lane.

Front-end kits for DesignWare IP on the TSMC 10nm process are available.