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The lowdown on MIPI D'PHY RX

Posted: 28 Sep 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Mobile Industry Processor Interface? MIPI? interoperability? D'Phy?

The Mobile Industry Processor Interface (MIPI) alliance is a non-profit organisation that establishes standards for hardware and software interfaces in mobile devices. Its vision is to develop the world's most comprehensive standard set of interface specifications for mobile and mobile influenced products which will maximise design reuse, drive innovation, reduce time to market and will help in interoperability of products from various companies.

MIPI D'Phy is a physical serial data communication layer on which the protocols like CSI (Camera Serial Interface), DSI (Display Serial Interface) runs. It physically connects the camera sensor to the application processor (for CSI) and application processor to the display device (for DSI) as shown in figure 1.

D'Phy is a high speed, low power, source synchronous physical layer which is best suited for power hungry battery operated devices due to its power efficient design. It includes in it both the high speed and low power modules which helps in achieving power efficiency. The payload data (image data) uses the high speed modules whereas the control and status information is send (between camera/display device and the application processor) with the help of low power modules(utilising low frequency signals). It has a peculiar ability of sending the high speed and low power data in the single packet burst. The low power modules help in achieving power savings and the high speed modules help in achieving the much needed higher bandwidth requirement for the High definition picture quality data signals.

Figure 1: Block Diagram of Mobile Phone depicting Camera and Display.

Architecture of D'Phy
In order to meet the high bandwidth requirement of HD quality images, MIPI D'Phy consists of one clock lane and has an option of configurable number of data lanes with a maximum of four lanes. The bandwidth can be increased by increasing the number of data lanes. By increasing the number of lanes, the same quantity of data can be transmitted on multiple lanes in lesser time. MIPI D'Phy uses forward source synchronous clock, which is used by all the data lanes of D'Phy receiver for capturing the high speed data signals.

Figure 2: Block Universal D'Phy lane.

In order to meet both the low power and high speed requirements, every data lane of universal D'Phy IP(as shown in the above figure) consists of low power transmitter (LP-TX), high speed transmitter (HS-TX), serialiser for transmitting MIPI D'Phy specific patterns and on receiving side it consists of low power receiver (LP RX), high speed receiver (HS-RX), deserialiser and a low power contention detector (LP-CD) for receiving those MIPI D'Phy specific data signals.

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