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The lowdown on MIPI D'PHY RX

Posted: 28 Sep 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Mobile Industry Processor Interface? MIPI? interoperability? D'Phy?

The clock lane consists of the low power transmitter (LP-TX), high speed transmitter (HS-TX) for transmitting MIPI D'Phy specific clock lane patterns and on receiver side it consists of low power receiver (LP RX), high speed receiver (HS-RX) and a low power contention detector (LP-CD) for receiving those MIPI D'Phy specific clock signals.

Every data lane (or clock lane) of the receiver is connected to the transmitter through two wires, Dp and Dn (or Clkp and Clkn). Both high speed and low power data transmission happens on these two wires connecting these two communicating modules.

The Low power module, an unterminated module, operate in single ended manner and work on 1.2V logic voltage. The data rate of low power signals, used for providing control and status information, is less than 10Mbps.

The high speed modules operate in a differential manner. They utilise the low voltage swing of the payload data signals to transfer the information (typical differential output swingDp C Dnof high speed signals is 200mV). It contains usually an on die termination, of value, typically 100? differential (between Dp and Dn).

Working of D'Phy
The image data captured by the camera sensor is processed by the MIPI transmitter to be transmitted over its multiple data lanes. The number of data lanes to be used for the transmission of data is configurable.

Depending on the number of data lanes to be used for data transmission, the image data is organised by the transmitter. The transmitter then serialises the data on each lane and transmits it to the corresponding receiving lanes.

For example, if two lanes are used, the first byte of payload data is sent over data lane 0 and second byte on data lane 1. Similarly, on the receiving side, the serial data from each data lane is converted into byte format with the help of deserialiser present in each receiving lane of the D'Phy. After this, the deserialzed bytes from each lane are merged together by the CSI controller.

Before the payload data of every HS burst on each lane, the transmitting D'Phy inserts a sync sequence (00011101) as shown in the below figure. This sync sequence is used by the data lanes of the receiving D'Phy to establish synchronisation with the high speed payload data. It is only when the synchronisation signal is properly decoded by the receiving D'Phy, the payload data is forwarded to the MIPI CSI 2 controller for further processing of the data.

Figure 3: Sync Sequence in the transmitted pattern.

As part of the initialisation of D'Phy, initially all the lanes are held at LP11 state (1.2V level) for a specified time. This LP11 state is also known as stop state. After this, for sending the image data, the transmitter drives a particular sequence on the receiver to enter the receiver lanes from the low power mode to high speed mode. The high speed entry sequence consists of driving LP11->LP01->LP00 (LP->HS transition) on the receiver lanes as shown in the following figure. On successful reception of this sequence the high speed receiver module enables its termination to receive the high speed differential data.

Now the high speed receiver termination has become active and the receiver starts to receive the high speed data from the transmitter. However, after LP->HS transition, the transmitter sends HS Zeros (V(Dn)>V(Dp)) for a specified amount of time to make sure that the receiver is enabled properly before any payload data is transmitted.

Once enabled, HS receiver continues to receive the data till it encounters the LP11 state on its lane. The LP11 state brings back the data lane from high speed mode to low power mode.

Figure 4: HS Burst on Data Lane depicting the LP to HS transition and HS Zero.

The payload data transmitted over the D'Phy data lane is in packet format. It could be either a long packet or a short packet. Long packet consists of 32 bit Packet header, payload data and 16 bit of packet footer. Short packet consists of 32 bit of packet header only.

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