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The lowdown on MIPI D'PHY RX

Posted: 28 Sep 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Mobile Industry Processor Interface? MIPI? interoperability? D'Phy?

After every HS burst the data lanes go to LP11 state. A single HS burst represents the image data corresponding to one of the horizontal line of an image and the LP11 state in-between the HS bursts represents the blanking periods. Because low power commands require signals to be send at lower frequency, this intermittent movements of D'Phy in LP and HS modes helps in reducing the overall power consumption.

When no data transfer is required, all the lanes are kept in ULPS mode (ultra-low-power mode). This is a special low power mode which helps in further reducing the power. ULPS mode is entered through a specific low power pattern. Once in the ULPS state all the lanes are driven low (0V). The ULPS entry pattern are different for clock and data lanes.


Timing relationship between differential clock and data
The high speed payload data from the transmitter is transmitted on both the edges of the High speed differential clock (DDR clock) as shown in the below figure. The high speed differential clock and the data transmitted from the transmitter are 90 degrees out of phase and with the data being transmitted first. This timing relationship between clock and data helps in achieving the setup and hold time requirements at the receiver data lanes.

Figure 5: Timing relationship between clock and data.

MIPI D'Phy as a physical serial communicating layer is gaining traction in the today's power hungry mobile and mobile related applications due to its low power consumption operation.

About the author
Love Gupta earned B.E in Electronics from Thapar University and joined Freescale in 2012 in Analogue Validation team. Love has been working on various projects and had validated multiple IPs.

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